Patents by Inventor Chia-Chuan CHANG
Chia-Chuan CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162094Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.Type: ApplicationFiled: January 5, 2024Publication date: May 16, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chuan CHIU, Jia-Chuan YOU, Chia-Hao CHANG, Chun-Yuan CHEN, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
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Publication number: 20240155185Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.Type: ApplicationFiled: November 9, 2022Publication date: May 9, 2024Inventors: Chia-Hao CHANG, You-Tsai JENG, Kai-Wen YEH, Yi-Cheng CHEN, Te-Chuan WANG, Kai-Wen CHENG, Chin-Lung LIN, Tai-Lai TUNG, Ko-Yin LAI
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Patent number: 11962847Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.Type: GrantFiled: November 9, 2022Date of Patent: April 16, 2024Assignee: MEDIATEK INC.Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
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Patent number: 11955515Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.Type: GrantFiled: July 28, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
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Publication number: 20240113199Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode structure over a channel region, wherein the gate electrode structure includes a gate dielectric layer disposed over the first channel region, a gate electrode disposed over the gate dielectric layer, and insulating spacers disposed over opposing sidewalls of the gate electrode, wherein the gate dielectric layer is disposed over opposing sidewalls of the gate electrode. An interlayer dielectric layer is formed over opposing sidewalls of the insulating spacers. The insulating spacers are removed from an upper portion of the opposing sidewalls of the gate electrode to form trenches between the opposing sidewalls of the upper portion of the gate electrode and the interlayer dielectric layer, and the trenches are filled with an insulating material.Type: ApplicationFiled: February 7, 2023Publication date: April 4, 2024Inventors: Jia-Chuan YOU, Chia-Hao Chang, Kuo-Cheng Chiang, Chin-Hao Wang
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Publication number: 20240096961Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Shih-Chuan CHIU, Tien-Lu LIN, Yu-Ming LIN, Chia-Hao CHANG, Chih-Hao WANG, Jia-Chuan YOU
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Patent number: 11916072Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.Type: GrantFiled: July 22, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230418256Abstract: A measuring unit is used to measure a specific dimension of a product feature within a time segment to generate a measured dimension value. A processing unit compares the measured dimension value with a standard dimension value to generate an offset value. A control unit generates a control instruction based on the offset value, and transmits the control instruction to a machine on which machining member that is used to form the product feature is installed, so that the machine performs tool compensation on the machining member according to the control instruction.Type: ApplicationFiled: December 2, 2022Publication date: December 28, 2023Inventors: TZU-CHI CHAN, CHIA-CHUAN CHANG, HAN-HUEI LIN, YI-HAO CHEN
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Patent number: 11330946Abstract: A dust collector comprises: a first container, a vacuum motor, a first-flow guiding unit, and a second flow-guiding unit; wherein the first container is set with a first tube-body, and the vacuum motor is set on a cover-body; wherein the motor is set with a filter, wherein the first flow-guiding unit and the second flow-guiding unit are respectively detachably combined with a second container and a third container; wherein the second flow-guiding unit is located in the first flow-guiding unit, and the first tube-body sucks in air, so that the dust and debris in the air enter the first container; wherein the air sequentially passes through the first flow-guiding unit and the second flow-guiding unit to form a vortex to make the fine dust fell into the second container and the third container; and the air is finally discharged by the vacuum motor after passes through the filter.Type: GrantFiled: October 7, 2019Date of Patent: May 17, 2022Inventor: Chia-Chuan Chang
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Publication number: 20210100414Abstract: A dust collector comprises: a first container, a vacuum motor, a first-flow guiding unit, and a second flow-guiding unit; wherein the first container is set with a first tube-body, and the vacuum motor is set on a cover-body; wherein the motor is set with a filter, wherein the first flow-guiding unit and the second flow-guiding unit are respectively detachably combined with a second container and a third container; wherein the second flow-guiding unit is located in the first flow-guiding unit, and the first tube-body sucks in air, so that the dust and debris in the air enter the first container; wherein the air sequentially passes through the first flow-guiding unit and the second flow-guiding unit to form a vortex to make the fine dust fell into the second container and the third container; and the air is finally discharged by the vacuum motor after passes through the filter.Type: ApplicationFiled: October 7, 2019Publication date: April 8, 2021Inventor: Chia-Chuan Chang
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Patent number: 8493794Abstract: A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a well region having a first conductive type. A first transistor and a second transistor having a second conductive type are disposed on the well region, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. The first transistor and the second transistor share a drain region, coupling to a bit line. A first source region of the first transistor and a second region of the second transistor are coupled to a first select line and a second line, respectively. A bit is stored in the first and second gates by controlling the first select line and the second line. A bit stored in the first and second gates is erased by controlling the first select line or the second line.Type: GrantFiled: July 15, 2011Date of Patent: July 23, 2013Assignee: Vanguard International Semiconductor CorporationInventors: Chia-Chuan Chang, Wei-Sung Chen, Chung-Ho Wu
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Patent number: 8477539Abstract: A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a substrate having a first conductive type. A first transistor, a second transistor and a select transistor having a second conductive type are disposed in the substrate, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. A source region of the first transistor is coupled to a bit line. A drain region of the second transistor and a gate of the select transistor are coupled to a select gate line. A drain region of the first transistor is coupled to a source region of the select transistor. A drain region of the select transistor is coupled to a select line.Type: GrantFiled: July 15, 2011Date of Patent: July 2, 2013Assignee: Vangaurd International Semiconductor CorporationInventors: Chia-Chuan Chang, Wei-Sung Chen, Chung-Ho Wu
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Publication number: 20130016567Abstract: A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a substrate having a first conductive type. A first transistor, a second transistor and a select transistor having a second conductive type are disposed in the substrate, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. A source region of the first transistor is coupled to a bit line. A drain region of the second transistor and a gate of the select transistor are coupled to a select gate line. A drain region of the first transistor is coupled to a source region of the select transistor. A drain region of the select transistor is coupled to a select line. A bit is stored in the first and second gates by controlling the bit line and the select gate line. A bit stored in the first and second gates is erased by controlling the bit line and the select gate line.Type: ApplicationFiled: July 15, 2011Publication date: January 17, 2013Inventors: Chia-Chuan CHANG, Wei-Sung Chen, Chung-Ho Wu
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Publication number: 20130016568Abstract: A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a well region having a first conductive type. A first transistor and a second transistor having a second conductive type are disposed on the well region, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. The first transistor and the second transistor share a drain region, coupling to a bit line. A first source region of the first transistor and a second region of the second transistor are coupled to a first select line and a second line, respectively. A bit is stored in the first and second gates by controlling the first select line and the second line. A bit stored in the first and second gates is erased by controlling the first select line or the second line.Type: ApplicationFiled: July 15, 2011Publication date: January 17, 2013Inventors: Chia-Chuan CHANG, Wei-Sung Chen, Chung-Ho Wu