Patents by Inventor Chia-Chun Huang

Chia-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962949
    Abstract: A method of performing air pollution estimation is provided. The method is to be implemented using a processor of a computer device and includes: generating a spectral image based on an original color image of an environment under test using a spectral transformation matrix; supplying the spectral image as an input into an estimating model for air pollution estimation; and obtaining an estimation result from the estimating model indicating a degree of air pollution of the environment under test.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: April 16, 2024
    Assignee: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Chia-Cheng Huang, Ting-Chun Men
  • Publication number: 20240115616
    Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240121899
    Abstract: An electronic device includes a substrate, a plurality of flexible circuit boards, a plurality of ICs and an insulator. The flexible circuit boards are disposed on the substrate. In a top view of the electronic device, the flexible circuit boards are overlapped with an edge of the substrate. The ICs are disposed on the substrate. The insulator is disposed on the flexible circuit boards and contacted the ICs, wherein the insulator has a first side and a second side opposite to the first side and the first side is closer to the edge than the second side. Along a first direction perpendicular to an extension direction of the edge, a first minimum distance between the second side and one of the ICs is less than a second minimum distance between the second side and one of the flexible circuit boards.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: Chin-Cheng Kuo, Chia-Chun Yang, Wen-Cheng Huang
  • Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Publication number: 20240107414
    Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN
  • Patent number: 11935981
    Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 19, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chu-Jih Su, Chia-Hsiang Chou, Wei-Chih Peng, Wen-Luh Liao, Chao-Shun Huang, Hsuan-Le Lin, Shih-Chang Lee, Mei Chun Liu, Chen Ou
  • Publication number: 20240088224
    Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
  • Publication number: 20240088307
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240086612
    Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240072459
    Abstract: An electrical connection structure including a first substrate, a first conductive pad, a second substrate, a second conductive pad, at least two through holes and a conductive material. The first conductive pad is disposed on the first substrate and includes a first top surface. The second conductive pad is disposed on the second substrate and includes a second top surface. The at least two through holes pass through the first substrate and expose portions of the second top surface. A portion of the conductive material is disposed within the at least two through holes, and the conductive material electrically connects the first conductive pad and the second conductive pad.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 29, 2024
    Applicant: InnoLux Corporation
    Inventors: Chia-Chun LIU, Hao-Jung HUANG
  • Publication number: 20190313262
    Abstract: A PDU session and QoS flow handling mechanism is proposed when a QoS flow of a PDU session does not have a mapping DRB after a handover or a service request procedure. If the QoS flow is associated with a default QoS rule, the UE can locally release the PDU session, initiate a PDU session release procedure, send a 5GSM status message with proper cause, or assume the PDU session is not reactivated. On the other hand, if the QoS flow is not associated with a default QoS rule, the UE can locally delete the QoS flow, delete the QoS flow by using a PDU session modification procedure, or send a 5GSM status message with proper cause.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 10, 2019
    Inventors: Chia-Chun Huang-Fu, Chi-Hsien Chen, Shang-Ru Mo
  • Patent number: 9241163
    Abstract: Methods, devices and systems that perform VC-2 decoding are disclosed. In an embodiment, a VC-2 decoder includes three parallel data paths including top-band, current-band and bottom-band data paths. The top-band data path performs variable length decoding (VLD), inverse-quantization (IQ) and inverse-DC-prediction (IDCP) processing of a top compressed data-band. The current-band data path performs VLD, IQ and IDCP processing of a current compressed data-band. The bottom-band data path performs VLD, IQ and IDCP processing of a bottom compressed data-band. Additionally, the decoder includes a three-level inverse discrete wavelet transform (IDWT) module to perform IDWT processing to synthesize decoded source pixel values in dependence on partially-decompressed top, current and bottom data-bands produced using the three parallel data paths.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: January 19, 2016
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Caizhang Zhou, Ting-Chung Chen, Chia-Chun Huang
  • Patent number: 6888392
    Abstract: A method and related circuitry for driving output signals of a chip is disclosed. The method includes driving output signals with an even number of inverter driving circuits, and keeping an equivalent load of each inverter of the driving circuits substantially identical by keeping impedances of each driving circuit substantially identical.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: May 3, 2005
    Assignee: VIA Technologies Inc.
    Inventors: Yi-Kuang Wei, Chia-Chun Huang, Chi-Ren Kuo
  • Publication number: 20040027176
    Abstract: A method and related circuitry for driving output signals of a chip is disclosed. The method includes driving output signals with an even number of inverter driving circuits, and keeping an equivalent load of each inverter of the driving circuits substantially identical by keeping impedances of each driving circuit substantially identical.
    Type: Application
    Filed: May 5, 2003
    Publication date: February 12, 2004
    Inventors: Yi-Kuang Wei, Chia-Chun Huang, Chi-Ren Kuo
  • Patent number: 6192075
    Abstract: Integrated circuit provides single-pass, real-time digital image encoding by digital signal processor for variable bit rate (VBR) control to improve decoded output quality. Possible peak bit rate range for multiple groups of pictures (GOP) and averaged bit rate limit encoded signal bit rate. Possible bit rate range constraint sets upper/lower range, which is pre-specified or dynamically adapted for current and future GOPs. Signal processor calculates perceptual weighting variable at macroblock level for multiple GOPs, nominal quantization parameters for multiple GOPs, quantization parameter associated at picture level, effective bit rate for each GOP, bit allocation for each picture, and total bit allocation for multiple GOPs. Variable rate signal is recordable in DVD or camcorder device.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: February 20, 2001
    Assignee: Stream Machine Company
    Inventors: Fure-Ching Jeng, Cheng-Tie Chen, Chia-Chun Huang