Patents by Inventor Chia-Chun Wu
Chia-Chun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972055Abstract: The disclosure provides an electronic device with a vibration function and a vibration driving method. The electronic device includes a processor and an audio player. The processor outputs an audio signal according to an application program, and executes an audio analysis module to analyze the audio signal. The audio player is coupled to the processor, and receives the audio signal. When the audio analysis module determines that the audio signal has a loudness with an audio frequency lower than a default frequency threshold according to an audio frequency distribution of the audio signal, the audio analysis module outputs a vibration drive signal according to the loudness of the audio signal.Type: GrantFiled: October 4, 2022Date of Patent: April 30, 2024Assignee: ASUSTeK COMPUTER INC.Inventors: Ta Chun Chou, Chih kun Chuang, Chia Yuan Wu
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Publication number: 20240135861Abstract: The present disclosure provides a display apparatus including an LED array. The display apparatus comprises a light emitting diode (LED) array, a power source, a controller, a PWM switch, and a current source module. The controller is configured to generate a control signal for controlling a first LED column during a scan period. The PWM switch is electrically connected between the first LED column and a second power level. The current source module is electrically connected between the first LED column and the second power level. The current source module is configured to provide a current flow with multiple levels. The PWM switch is controlled based on a first portion of the control signal, and the amount of the current flow provided by the current source module in the scan period depends on a second portion of the control signal.Type: ApplicationFiled: October 23, 2022Publication date: April 25, 2024Inventors: Tsun-I WANG, Ching-Chun WU, Chia-Liang YANG
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Patent number: 11951638Abstract: A method for determining a standard depth value of a marker includes obtaining a maximum depth value of the marker. A reference depth value of the marker is obtained based on a depth image of the marker, and a Z-axis coordinate value of the marker is obtained based on a color image of the marker. When the reference depth value and the Z-axis coordinate value are both less than the maximum depth value, and a difference between the reference depth value and the Z-axis coordinate value is not greater than 0, the depth reference value is set as the standard depth value of the marker; and when the difference is greater than 0, the Z-axis coordinate value is set as the standard depth value of the marker.Type: GrantFiled: December 29, 2020Date of Patent: April 9, 2024Assignee: Chiun Mai Communication Systems, Inc.Inventors: Tung-Chun Hsieh, Chung-Wei Wu, Chih-Wei Li, Chia-Yi Lin
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Patent number: 11955154Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.Type: GrantFiled: May 16, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
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Patent number: 11948920Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 11945907Abstract: Provided are an LCP film and a laminate comprising the same. The LCP film is made of an LCP resin comprising a structural unit represented by Formula (1): -L1-Ar-L2- (1), wherein -L1- and -L2- are respectively —O— or —CO—; —Ar— is an arylene group. Formula (1) comprises structural units Based on a total molar number of the structural unit represented by Formula (1), a molar number of the structural unit represented by Formula (I) is in the range from 15 mole % to mole %, and a sum of molar numbers of the structural units represented by Formulae (I) and (II) is in the range from 80 mole % to 100 mole %. The LCP film has a thickness and a transmittance, wherein when values of the thickness (in ?m) and the transmittance are put into Formula (III), the obtained value is from 0.055 to 0.090. Formula (III): Log(1/TT %)/(Thickness)0.5.Type: GrantFiled: December 18, 2020Date of Patent: April 2, 2024Assignee: CHANG CHUN PLASTICS CO., LTD.Inventors: An-Pang Tu, Chia-Hung Wu, Chien-Chun Chen
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Patent number: 11931187Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.Type: GrantFiled: March 16, 2018Date of Patent: March 19, 2024Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung UniversityInventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
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Publication number: 20240086609Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.Type: ApplicationFiled: February 16, 2023Publication date: March 14, 2024Inventors: Cheng-YU LIN, Chia Chun WU, Han-Chung CHANG, Chih-Liang CHEN
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Publication number: 20240084447Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Peng-Cheng Hong, Jun-Liang Pu, W.L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
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Publication number: 20240088307Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Patent number: 11929318Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.Type: GrantFiled: May 10, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Patent number: 11929328Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.Type: GrantFiled: January 4, 2021Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yang Wu, Shiu-Ko JangJian, Ting-Chun Wang, Yung-Si Yu
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Patent number: 11926698Abstract: Provided are a liquid crystal polymer film (LCP film) and a laminate comprising the same. The LCP film has a first surface and a second surface opposite each other, and the first surface has an arithmetical mean height of a surface (Sa) less than 0.32 ?m. The LCP film with proper Sa is suitable to be stacked with a metal foil, such that a laminate comprising the LCP film can have an advantage of low insertion loss.Type: GrantFiled: December 18, 2020Date of Patent: March 12, 2024Assignee: CHANG CHUN PLASTICS CO., LTD.Inventors: An-Pang Tu, Chia-Hung Wu, Chien-Chun Chen
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Publication number: 20240079332Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.Type: ApplicationFiled: November 8, 2023Publication date: March 7, 2024Inventors: Chia-Yang Wu, Shiu-Ko JangJian, Ting-Chun Wang, Yung-Si Yu
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Patent number: 11920238Abstract: A method of making a sealing article that includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.Type: GrantFiled: July 22, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Peng-Cheng Hong, Jun-Liang Pu, W. L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
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Patent number: 11916077Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.Type: GrantFiled: May 24, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
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Publication number: 20230290766Abstract: An integrated circuit includes a first and second active region extending in a first direction, and a floating gate, a first dummy gate, a first conductor and a second conductor extending in the second direction. The floating gate is electrically floating. The first dummy gate is separated from the floating gate in the second direction. The dummy gate and the floating gate separate a first cell that corresponds to a first transistor from a second cell that corresponds to a second transistor. The first and second conductors are separated from each other in the first direction, and overlap the second active region. The first and second conductors are electrically coupled to a corresponding source/drain of the second active region, and are configured to supply a same signal/voltage to the corresponding source/drain of the second active region. The floating gate is between the first and second conductors.Type: ApplicationFiled: July 5, 2022Publication date: September 14, 2023Inventors: Chia Chun WU, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Yung-Chen CHIEN
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Publication number: 20230261002Abstract: An IC device includes first and second power rails extending in a first direction and carrying one of a power supply or reference voltage, a third power rail extending between the first and second power rails and carrying the other of the power supply or reference voltage, and a plurality of transistors including first through fourth active areas extending between the first and second power rails, a plurality of gate structures extending perpendicularly to the first direction, and first and second conductive segments extending in the second direction across the third power rail. Each of the second and third active areas is adjacent to the third power rail, each of the first and second conductive segments is electrically connected to S/D structures in each of the second and third active areas, and the plurality of transistors is configured as one of an AOI, an OAI, or a four-input NAND gate.Type: ApplicationFiled: May 20, 2022Publication date: August 17, 2023Inventors: I-Wen WANG, Chia-Chun WU, Hui-Zhong ZHUANG, Yung-Chen CHIEN, Jerry Chang Jui KAO, Xiangdong CHEN
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Patent number: 11644998Abstract: A method for managing distributed storage implemented in a server includes obtaining files to be stored from a user; performing processing for distribution on the files to be stored; determine a storage requirement of the files to be stored, wherein the storage requirement can comprise file storage and object storage; storing the distributed files into a plurality of storage areas through a distributed storage unit when the storage requirement of the files to be stored is determined to be the file storage; and storing the distributed files into the plurality of storage areas through a distributed storage unit and an object storage unit when the storage requirement of the files to be stored is determined to be the file storage.Type: GrantFiled: August 12, 2021Date of Patent: May 9, 2023Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: Chia-Chun Wu
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Publication number: 20220050596Abstract: A method for managing distributed storage implemented in a server includes obtaining files to be stored from a user; performing processing for distribution on the files to be stored; determine a storage requirement of the files to be stored, wherein the storage requirement can comprise file storage and object storage; storing the distributed files into a plurality of storage areas through a distributed storage unit when the storage requirement of the files to be stored is determined to be the file storage; and storing the distributed files into the plurality of storage areas through a distributed storage unit and an object storage unit when the storage requirement of the files to be stored is determined to be the file storage.Type: ApplicationFiled: August 12, 2021Publication date: February 17, 2022Inventor: CHIA-CHUN WU