Patents by Inventor Chia-Chun YANG

Chia-Chun YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12147119
    Abstract: An electronic device is provided. The electronic device includes a frame, a backlight module, a working panel, and a spacer. The backlight module is disposed in the frame. The working panel is disposed on the frame. The spacer is disposed between the frame and the working panel. At least a portion of the working panel and at least a portion of the spacer are in direct contact with an adhesive.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 19, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Wen-Cheng Huang, Ting-Sheng Chen, Chia-Chun Yang, Chin-Cheng Kuo
  • Publication number: 20240379444
    Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
    Type: Application
    Filed: July 14, 2024
    Publication date: November 14, 2024
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
  • Patent number: 12132011
    Abstract: An integrated circuit device includes a substrate; an integrated circuit region on the substrate, said integrated circuit region comprising a dielectric stack; a seal ring disposed in said dielectric stack and around a periphery of the integrated circuit region; a trench around the seal ring and exposing a sidewall of the dielectric stack; and a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: October 29, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin, Chu-Chun Chang
  • Publication number: 20240355983
    Abstract: A display apparatus includes a driving backplane and a light emitting component. The driving backplane has a first pad and a second pad. The light emitting component is disposed on the driving backplane. The light emitting component includes a first semiconductor layer, a second semiconductor layer, an active layer, a first electrode, a second electrode, a first solder and a second solder. The first solder and the second solder of the light-emitting component are respectively disposed on the first pad and the second pad of the driving backplane and electrically connected to the first pad and the second pad respectively. A volume of the first solder is larger than a volume of the second solder, and an area of the first pad is smaller than an area of the second pad.
    Type: Application
    Filed: December 13, 2023
    Publication date: October 24, 2024
    Inventors: Chia-Hui Pai, Wen-Hsien Tseng, Chien-Hung Kuo, Wei-Chieh Chen, Kuan-Yi Lee, Chih-Chun Yang
  • Publication number: 20240355960
    Abstract: A light emitting element substrate includes a substrate and a light emitting element disposed on the substrate and including first and second semiconductor layers, an active layer, first and second electrodes, and first and second solders. The second semiconductor layer is disposed opposite to the first semiconductor layer. The active layer is disposed between the first and second semiconductor layers. The first and second electrodes are electrically connected to the first and second semiconductor layers respectively. The first and second solders are respectively disposed on and electrically connected to the first and second electrodes respectively. The first electrode includes a first under barrier pattern. The first solder covers the first under barrier pattern. A projection area of the first solder on the substrate is greater than a projection area of the first under barrier pattern on the substrate. A display apparatus is provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: October 24, 2024
    Applicant: AUO Corporation
    Inventors: Chia-Hui Pai, Wen-Hsien Tseng, Chien-Hung Kuo, Wei-Chieh Chen, Kuan-Yi Lee, Chih-Chun Yang
  • Publication number: 20240345428
    Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue disposed in the peripheral region and overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue extends along an extension direction parallel to the first edge, and along the extension direction, a sum of lengths of the first conductive glue and the second conductive glue is less than a length of the insulating glue.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Inventors: Wen-Cheng HUANG, Bi-Ly LIN, Chia-Chun YANG, Ying-Jung WU, Chien-Wei TSENG
  • Publication number: 20240332085
    Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Meng Jhe Tsai, Hong-Jie Yang, Meng-Chun Chang, Hao Chiang, Chia-Ying Lee, Huan-Just Lin, Chuan Chang
  • Patent number: 12091677
    Abstract: The present invention provides a carboxylated nanodiamond-mediated CRISPR-Cas9 delivery system for gene editing comprising nanodiamond (ND) particles as the carriers of CRISPR-Cas9 components designed to introduce the mutation in a given gene for repairing a tissue damage.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: September 17, 2024
    Assignees: Taipei Veterans General Hospital, National Chiao Tung University, National Cheng Kung University
    Inventors: Shih-Hwa Chiou, Tien-Chun Yang, Chia-Ching Chang, Yon-Hua Tzeng
  • Patent number: 12087712
    Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.
    Type: Grant
    Filed: March 19, 2023
    Date of Patent: September 10, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin, Chu-Chun Chang
  • Publication number: 20240296890
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Patent number: 12080604
    Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
  • Patent number: 12044914
    Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge and a second edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue is disposed in the peripheral region and extends along an extension direction parallel to the first edge, and along the extension direction, a first distance between the first conductive glue and the second edge is greater than a second distance between the second conductive glue and the second edge.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: July 23, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Wen-Cheng Huang, Bi-Ly Lin, Chia-Chun Yang, Ying- Jung Wu, Chien-Wei Tseng
  • Patent number: 12040233
    Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng Jhe Tsai, Hong-Jie Yang, Meng-Chun Chang, Hao Chiang, Chia-Ying Lee, Huan-Just Lin, Chuan Chang
  • Publication number: 20240219776
    Abstract: An electronic device is provided. The electronic device includes a frame, a working panel, a case, and an adhesive material. The frame includes a side wall and a back plate. The working panel is disposed on the back plate. The case is disposed on the frame and adjacent to the working panel. The adhesive material is disposed on the case. The side wall has an outer surface facing away from the working panel. In a cross-section view of the electronic device, a portion of the adhesive material is in contact with the outer surface of the side wall of the frame, and a length of the adhesive material is greater than or equal to 50% of a length of the side wall of the frame along an extension direction.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Inventors: Wen-Cheng HUANG, Ting-Sheng CHEN, Chia-Chun YANG, Chin-Cheng KUO
  • Publication number: 20240183082
    Abstract: A method for manufacturing an elastic fiber and the elastic fiber are provided. The method includes: providing a thermoplastic polyester elastomer; drying the thermoplastic polyester elastomer; melting the thermoplastic polyester elastomer by an extruder to form a melt; extruding the melt by a spinneret plate to form a plurality of filamentous streams; feeding the filamentous streams into a spinning channel for cooling and curing to form a plurality of monofilaments; and bundling and oiling the monofilaments by an oil wheel, after extending and guiding the monofilaments by a first godet roller and a second godet roller, and winding the monofilaments by a winder to obtain a thermoplastic polyester elastic fiber.
    Type: Application
    Filed: October 27, 2023
    Publication date: June 6, 2024
    Inventors: CHIH-YI LIN, KUO-KUANG CHENG, LI-YUAN CHEN, CHI-WEI CHANG, CHIA-CHUN YANG
  • Publication number: 20240121899
    Abstract: An electronic device includes a substrate, a plurality of flexible circuit boards, a plurality of ICs and an insulator. The flexible circuit boards are disposed on the substrate. In a top view of the electronic device, the flexible circuit boards are overlapped with an edge of the substrate. The ICs are disposed on the substrate. The insulator is disposed on the flexible circuit boards and contacted the ICs, wherein the insulator has a first side and a second side opposite to the first side and the first side is closer to the edge than the second side. Along a first direction perpendicular to an extension direction of the edge, a first minimum distance between the second side and one of the ICs is less than a second minimum distance between the second side and one of the flexible circuit boards.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: Chin-Cheng Kuo, Chia-Chun Yang, Wen-Cheng Huang
  • Publication number: 20240053627
    Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge and a second edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue is disposed in the peripheral region and extends along an extension direction parallel to the first edge, and along the extension direction, a first distance between the first conductive glue and the second edge is greater than a second distance between the second conductive glue and the second edge.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 15, 2024
    Inventors: Wen-Cheng HUANG, Bi-Ly LIN, Chia-Chun YANG, Ying- Jung WU, Chien-Wei TSENG
  • Patent number: 11889627
    Abstract: A display device includes a first substrate, a second substrate, a plurality of drive ICs and at least one flexible circuit board. The first substrate has a first region and a second region near to the first region. The second substrate is disposed on the first region and has a lateral side. The plurality of drive ICs are disposed on the second region and arranged along the lateral side. The at least one flexible circuit board is disposed on the second region and disposed correspondingly to the lateral side. Wherein in a top view of the display device, each of the plurality of drive ICs does not overlap with the at least one flexible circuit board in a direction perpendicular to an extending direction of the lateral side.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 30, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Chin-Cheng Kuo, Chia-Chun Yang, Wen-Cheng Huang
  • Publication number: 20240026362
    Abstract: Provided are interfering RNAs (e.g., siRNAs) targeting SARS-CoV (e.g., the POL, Spike, Helicase, or Envelop gene thereof) and therapeutic uses thereof for inhibiting SARS-CoV infection and/or treating diseases associated with the infection (e.g., COVID-19).
    Type: Application
    Filed: December 3, 2021
    Publication date: January 25, 2024
    Applicants: MICROBIO (SHANGHAI) CO. LTD., ONENESS BIOTECH CO. LTD.
    Inventors: Yi-Chung CHANG, Chi-Fan YANG, Yi-Fen CHEN, Chia-Chun YANG, Yuan-Lin CHOU
  • Patent number: 11835805
    Abstract: An electronic device includes a first substrate; a second substrate arranged opposite to the first substrate; a first electrode layer disposed on the first substrate; a display medium layer disposed between the first electrode layer and the second substrate; and a first metal element, wherein the first metal element is fixed on the first electrode layer through a conductive glue and an insulating glue; wherein in a normal direction of the first substrate, the conductive glue and the insulating glue are overlapped.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: December 5, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Wen-Cheng Huang, Bi-Ly Lin, Chia-Chun Yang, Ying-Jung Wu, Chien-Wei Tseng