Patents by Inventor Chia-Chung Wang

Chia-Chung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11189726
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
  • Publication number: 20210284890
    Abstract: A method of fabricating a grinding tool includes providing an abrasive particle, and cutting the abrasive particle with a laser beam so that the cut abrasive particle has four tips adjacent to one another, a cavity of a generally cross shape extending between the four tips, and a material discharge surface at an end of the cavity. The laser beam is applied along a plurality of parallel first cutting lines and a plurality of parallel second cutting lines, the second cutting lines intersecting the first cutting lines, at least the first cutting lines being grouped into a first, a second and a third region, the second region being located between the first and third regions, a number of cutting passes repeated along each of the first cutting lines in each of the first and third regions increasing as the first cutting line is nearer to the second region, and the laser beam repeating a plurality of cutting passes along each of the first cutting lines in the second region.
    Type: Application
    Filed: June 2, 2021
    Publication date: September 16, 2021
    Inventors: Jui-Lin CHOU, Chia-Feng CHIU, Chin-Chung CHOU, Hsin-Chun WANG
  • Publication number: 20210289678
    Abstract: An interconnect substrate includes a lower-modulus buffer material disposed around a thermally conductive base and a higher-modulus crack stopper disposed over the buffer material. By the difference of the elastic modulus between the crack stopper and the buffer material, thermo-mechanical induced stress can be absorbed in the buffer material, and crack propagation would be arrested by the crack stopper to ensure reliability of a routing trace which is deposited on the crack stopper and electrically coupled to vertical connecting elements in the buffer material. Further, the crack stopper can have low dissipation factor to ensure a lower rate of energy loss which is beneficial to high frequency applications.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Charles W. C. LIN, Chia-Chung WANG
  • Patent number: 10804205
    Abstract: The interconnect substrate mainly includes a stiffener, a core layer, a warp balancer and a routing circuitry. The stiffener has an elastic modulus higher than 100 GPa and is laterally surrounded by the core layer. The warp balancer is disposed over the top surface of the core layer and laterally surrounds a cavity aligned with the stiffener. The routing circuitry is disposed under the bottom surfaces of the stiffener and the core layer and electrically connected to the stiffener. By the high modulus of the stiffener, local thermo-mechanical stress induced by un-even thickness can be counterbalanced. Furthermore, adjusting the ratio of the stiffener thickness to the cavity dimension can maintain the cavity area stiffness and modulate the global flatness.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 13, 2020
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20200146192
    Abstract: The semiconductor assembly includes a semiconductor chip, a first wiring structure and a second wiring structure. The second wiring structure includes a warp balancer, a core layer, a top build-up layer and a bottom build-up layer. The warp balancer is laterally surrounded by the core layer and preferably has an elastic modulus higher than 100 GPa. The top and the bottom build-up layers are electrically connected to each other through the warp balancer or the core layer therebetween. The first wiring structure is disposed over the top build-up layer through connecting joints superimposed over the warp balancer. By the high modulus of the warp balancer, local thermo-mechanical stress can be counterbalanced to suppress warping and bending of the first and second wiring structures. Furthermore, mounting the first wiring structure over the second wiring structure can provide staged fan-out routing for the chip to improve routing efficiency and production yield.
    Type: Application
    Filed: December 26, 2019
    Publication date: May 7, 2020
    Inventors: Charles W. C. LIN, Chia-Chung WANG
  • Publication number: 20200135630
    Abstract: The interconnect substrate includes etching stoppers within a cavity and a plurality of metal leads disposed around the cavity. The cavity is formed by etching a sacrificial metal slug of a leadframe and laterally surrounded by a resin compound. The etching stoppers are deposited in pits of the metal slug and contact a routing circuitry. By removal of the metal slug, the etching stoppers are exposed from the cavity to provide electrical contacts for device connection within cavity. Due to high etch resistance of the etching stoppers, the integrity of the electrical contacts can be ensured during the cavity formation. As a result, a semiconductor device can be face-down disposed in the cavity and electrically connected to the reliable electrical contacts at the floor of the cavity.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Inventors: Charles W. C. LIN, Chia-Chung WANG
  • Publication number: 20200091116
    Abstract: A semiconductor assembly having heat dissipation characteristics includes stacked semiconductor chips thermally conductible to a thermal pad of an interconnect substrate and electrically connected to the interconnect substrate through bonding wire. The bonding wires extending from a primary routing circuitry in between the stacked chips can accommodate the height difference between the stacked chips and the interconnect substrate. These wires can also effectively compensate for the thermal expansion mismatch between the stacked chips and the interconnect substrate, thereby allowing a higher manufacturing yield and better reliability.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Inventors: Charles W. C. LIN, Chia-Chung WANG
  • Patent number: 10546808
    Abstract: The wiring substrate includes a cavity and a plurality of metal leads disposed around the cavity. The metal leads are bonded with a resin compound and provide horizontal and vertical routing for a semiconductor device to be disposed in the cavity. The resin compound fills in spaces between the metal leads and surrounds the cavity and provides a dielectric platform for a re-distribution layer or a build-up circuitry optionally deposited thereon.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: January 28, 2020
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20190333850
    Abstract: A wiring board includes an electrical isolator or an interconnect element incorporated with a core substrate or metal leads and a bridging element straddling over interfaces between two adjoined surfaces to electrically connect a routing circuitry on the electrical isolator or on the interconnect element to another routing circuitry on the core substrate or to the metal leads. As the bridging element offers a reliable connecting channel without direct attachment to the interfaces, any cracking or delamination across the interfaces will not affect the routing integrity.
    Type: Application
    Filed: June 12, 2019
    Publication date: October 31, 2019
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10446526
    Abstract: A face-to-face semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, the semiconductor device is face-to-face electrically coupled to another semiconductor device through a buildup circuitry therebetween.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 15, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10420204
    Abstract: A method of making a wiring board having an electrical isolator and metal posts incorporated in a resin core is characterized by the provision of moisture inhibiting caps covering interfaces between the electrical isolator/metal posts and a surrounding plastic material. In a preferred embodiment, the electrical isolator and metal posts are bonded to the resin core by an adhesive substantially coplanar with the metal films on the electrical isolator, the metal posts and the metal layers on two opposite sides of the resin core at smoothed lapped top and bottom surfaces so that a metal bridge can be deposited on the adhesive at the smoothed lapped bottom surface to completely cover interfaces between the electrical isolator/metal posts and the surrounding plastic material. Conductive traces are also deposited on the smoothed lapped top surface to provide electrical contacts for chip connection and electrically coupled to the metal posts.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: September 17, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20190267307
    Abstract: The wiring board mainly includes a heat dissipation slug, core substrate and a modified binding matrix. The modified binding matrix provides mechanical bonds between the heat dissipation slug and the core substrate disposed about the peripheral sidewall of the heat dissipation slug. The modified binding matrix contains low CTE modulators dispensed in a resin adhesive to alleviate resin internal expansion and shrinkage, thereby significantly reducing the risk of the resin cracking.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 29, 2019
    Inventors: Charles W. C. LIN, Chia-Chung WANG
  • Patent number: 10361151
    Abstract: A wiring board includes a low CTE (coefficient of thermal expansion) and high thermal conductivity isolator incorporated in a resin laminate by an adhesive and a bridging element disposed over the isolator and the resin laminate and electrically coupled to a first routing circuitry on the isolator and a second routing circuitry on the resin laminate. The isolator provides CTE-compensated contact interface for a semiconductor chip to be assembled thereon, and also provides primary heat conduction for the chip. The bridging element offers a reliable connecting channel for interconnecting contact pads on the isolator to terminal pads on the resin laminate.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: July 23, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10354984
    Abstract: A semiconductor assembly includes an encapsulated device and a thermally enhanced device face-to-face mounted together through first and second routing circuitries and a heat spreader that provides thermal dissipation and electromagnetic shielding. The encapsulated device has a first semiconductor chip sealed in an encapsulant, whereas the thermally enhanced device has a second semiconductor chip thermally conductible to a shielding lid of the heat spreader and laterally surrounded by posts of the heat spreader. The first and second semiconductor chips are mounted on two opposite sides of the first routing circuitry, and the second routing circuitry is disposed on the shielding lid and electrically coupled to the first routing circuitry by bumps. The first and second routing circuitries provide staged fan-out routing for the first and second semiconductor chips.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: July 16, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20190182997
    Abstract: The leadframe substrate mainly includes a modulator, a plurality of metal leads, a resin layer and a crack inhibiting structure. The resin layer provides mechanical bonds between the modulator and the metal leads disposed about peripheral sidewalls of the modulator. The crack inhibiting structure includes a continuous interlocking fiber sheet that covers the modulator/resin interfaces, so that the segregation induced along the modulator/resin interfaces or cracks formed within the resin layer can be prevented or restrained from extending to the top surfaces, thereby ensuring the signal integrity of the flip chip assembly.
    Type: Application
    Filed: February 19, 2019
    Publication date: June 13, 2019
    Inventors: Charles W. C. LIN, Chia-Chung WANG
  • Patent number: 10306777
    Abstract: A wiring board with dual stiffeners and integrated dual routing circuitries is characterized in that first and second routing circuitries are positioned within and beyond a through opening of a first stiffener, respectively, and an array of vertical connecting channels are disposed on the second routing circuitry and laterally surrounded by a second stiffener. The mechanical robustness of the first and second stiffeners can prevent the wiring board from warping. The vertical connecting channels can offer electrical contacts for next-level connection. The first routing circuitry, positioned within the through opening of the first stiffener, can provide primary fan-out routing, whereas the second routing circuitry not only provides further fan-out wiring structure for the first routing circuitry, but also mechanically binds the first routing circuitry with the first stiffener.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 28, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10269722
    Abstract: A wiring board includes an electronic component laterally surrounded by a leadframe, and first and second buildup circuitries disposed beyond the space laterally surrounded by the leadframe and extending over the leadframe. The electronic component includes a first routing circuitry, an encapsulant, optionally an array of vertical connecting elements and optionally a second routing circuitry integrated together. The first routing circuitry provides primary routing for the semiconductor device, whereas the first and second buildup circuitries not only provides further routing, but also mechanically binds the electronic component with the leadframe. The leadframe provides electrical connection between the first buildup circuitry and the second buildup circuitry.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: April 23, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10242964
    Abstract: The wiring substrate includes a cavity and a plurality of vertical connecting channels disposed around the cavity. The vertical connecting channels are bonded with a resin compound and electrically connected to a routing circuitry or a conducting layer under the cavity. The bottom of the cavity is covered by a dielectric layer of the routing circuitry or the resin compound, and an aperture is formed through the dielectric layer of the routing circuitry or the resin compound to be communicated with the cavity. As a result, a semiconductor device can be face-down disposed in the cavity and electrically connected to the routing circuitry or the conducting layer by bonding wires extending through the aperture.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 26, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20190090391
    Abstract: An interconnect substrate mainly includes a first wiring layer, vertical connecting elements, a stress modulator, a buffering layer and a resin layer. The resin layer bonds sidewalls of the stress modulator and lateral surface of the vertical connecting elements laterally surrounding the stress modulator. The first wiring layer includes interconnect pads in the buffering layer and routing traces in the resin layer. The routing traces are integrated with the interconnect pads and electrically coupled to the vertical connecting elements. The interconnect pads are superimposed over and spaced from the stress modulator by the buffering layer, so that bumps for device connection can be mounted at the area covered by the stress modulator, thereby avoiding cracking of the bumps.
    Type: Application
    Filed: November 16, 2018
    Publication date: March 21, 2019
    Inventors: Charles W. C. LIN, Chia-Chung WANG
  • Patent number: 10217710
    Abstract: A wiring board includes an electronic component laterally surrounded by a stiffener, and a third routing circuitry disposed beyond the space laterally surrounded by the stiffener and extends over the stiffener. The electronic component includes a first routing circuitry, an encapsulant, an array of vertical connecting elements and a second routing circuitry integrated together. The mechanical robustness of the stiffener can prevent the wiring board from warping. The embedded semiconductor device is electrically coupled to the first routing circuitry and surrounded by the vertical connecting elements in electrical connection with the first and second routing circuitries. The first routing circuitry provides primary fan-out routing for another semiconductor device to be assembled on the wiring board, whereas the third routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the electronic component with the stiffener.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 26, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang