Abstract: A semiconductor packaging substrate comprises a crack-inhibiting dielectric frame and a plurality of interconnect units each including electrically conductive posts and an interfacial dielectric layer. These interconnect units are formed within separate compartments defined by the crack-inhibiting dielectric frame. The interfacial dielectric layer laterally covers and surrounds sidewalls of the electrically conductive posts. By using a crack-inhibiting dielectric frame instead of a conventional metal frame, structural warpage can be suppressed during the application of the interfacial dielectric layer.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: The present invention discloses a hacking detection method, including: deploying a plurality of trap IP addresses in a trap IP address list; collecting access logs from a plurality of network devices to create a connection record list, wherein the connection record list includes a plurality of connection records; and comparing the trap IP address list and the connection record list to obtain a suspicious source list. The suspicious source list includes a plurality of suspicious source IP addresses. The suspicious source IP addresses match a portion of the trap IP addresses in the trap IP address list.

Abstract: A lead frame substrate includes a circuitry layer, terminals, a warpage inhibiting dielectric layer and a stiffening dielectric layer. The circuitry layer extends laterally from the terminals and has an external surface facing away from the stiffening dielectric layer and an inner surface facing in and spaced from a top surface of the stiffening dielectric layer by the warpage inhibiting dielectric layer. The stiffening dielectric layer can serve as a robust platform to support the lateral extension of a circuitry layer and avoid crack propagation through the stiffening dielectric layer into the circuitry layer. The warpage inhibiting dielectric layer can absorb stress and alleviate warpage of the structure during bonding the stiffening dielectric layer to a lead frame with the terminals.

Abstract: A terminal structure includes an electrically conductive post, an electrically conductive flange, and a stress buffer. The electrically conductive post has a bottom surface at a first level and an upper sidewall laterally covered by the stress buffer. The stress buffer has a bottom surface at a second level between the top surface and the bottom surface of the electrically conductive post. The electrically conductive flange extends laterally from the upper sidewall of the electrically conductive post to an outer peripheral edge thereof, and has a depression surface at a third level between the top surface and the bottom surface of the electrically conductive post. Accordingly, the terminal structure has multi-level staggered configuration and is advantageous to achieving the desired wetting height for robust visual inspection and improving primary and secondary board-level reliability.

Abstract: A semiconductor assembly includes a top substrate and a base substrate attached to top and bottom electrode layers of a semiconductor device, respectively. The top substrate includes an electrode connection plate thermally conductible with and electrically connected to the top electrode layer of the semiconductor device and vertical posts protruding from the electrode connection plate and electrically connected to the base substrate. The base substrate includes an electrode connection slug embedded in a dielectric layer and thermally conductible with and electrically connected to the bottom electrode layer of the semiconductor device and first and second routing circuitries deposited on two opposite surfaces of the dielectric layer, respectively, and electrically connected to each other.

Abstract: The leadframe substrate mainly includes a modulator, a plurality of metal leads, a resin layer and a crack inhibiting structure. The resin layer provides mechanical bonds between the modulator and the metal leads disposed about peripheral sidewalls of the modulator. The crack inhibiting structure includes a continuous interlocking fiber sheet that covers the modulator/resin interfaces, so that the segregation induced along the modulator/resin interfaces or cracks formed within the resin layer can be prevented or restrained from extending to the top surfaces, thereby ensuring the signal integrity of the flip chip assembly.

Abstract: An interconnect substrate includes a lower-modulus buffer material disposed around a thermally conductive base and a higher-modulus crack stopper disposed over the buffer material. By the difference of the elastic modulus between the crack stopper and the buffer material, thermo-mechanical induced stress can be absorbed in the buffer material, and crack propagation would be arrested by the crack stopper to ensure reliability of a routing trace which is deposited on the crack stopper and electrically coupled to vertical connecting elements in the buffer material. Further, the crack stopper can have low dissipation factor to ensure a lower rate of energy loss which is beneficial to high frequency applications.

Abstract: The interconnect substrate mainly includes a stiffener, a core layer, a warp balancer and a routing circuitry. The stiffener has an elastic modulus higher than 100 GPa and is laterally surrounded by the core layer. The warp balancer is disposed over the top surface of the core layer and laterally surrounds a cavity aligned with the stiffener. The routing circuitry is disposed under the bottom surfaces of the stiffener and the core layer and electrically connected to the stiffener. By the high modulus of the stiffener, local thermo-mechanical stress induced by un-even thickness can be counterbalanced. Furthermore, adjusting the ratio of the stiffener thickness to the cavity dimension can maintain the cavity area stiffness and modulate the global flatness.

Abstract: The semiconductor assembly includes a semiconductor chip, a first wiring structure and a second wiring structure. The second wiring structure includes a warp balancer, a core layer, a top build-up layer and a bottom build-up layer. The warp balancer is laterally surrounded by the core layer and preferably has an elastic modulus higher than 100 GPa. The top and the bottom build-up layers are electrically connected to each other through the warp balancer or the core layer therebetween. The first wiring structure is disposed over the top build-up layer through connecting joints superimposed over the warp balancer. By the high modulus of the warp balancer, local thermo-mechanical stress can be counterbalanced to suppress warping and bending of the first and second wiring structures. Furthermore, mounting the first wiring structure over the second wiring structure can provide staged fan-out routing for the chip to improve routing efficiency and production yield.

Abstract: The interconnect substrate includes etching stoppers within a cavity and a plurality of metal leads disposed around the cavity. The cavity is formed by etching a sacrificial metal slug of a leadframe and laterally surrounded by a resin compound. The etching stoppers are deposited in pits of the metal slug and contact a routing circuitry. By removal of the metal slug, the etching stoppers are exposed from the cavity to provide electrical contacts for device connection within cavity. Due to high etch resistance of the etching stoppers, the integrity of the electrical contacts can be ensured during the cavity formation. As a result, a semiconductor device can be face-down disposed in the cavity and electrically connected to the reliable electrical contacts at the floor of the cavity.

Abstract: A semiconductor assembly having heat dissipation characteristics includes stacked semiconductor chips thermally conductible to a thermal pad of an interconnect substrate and electrically connected to the interconnect substrate through bonding wire. The bonding wires extending from a primary routing circuitry in between the stacked chips can accommodate the height difference between the stacked chips and the interconnect substrate. These wires can also effectively compensate for the thermal expansion mismatch between the stacked chips and the interconnect substrate, thereby allowing a higher manufacturing yield and better reliability.

Abstract: The wiring substrate includes a cavity and a plurality of metal leads disposed around the cavity. The metal leads are bonded with a resin compound and provide horizontal and vertical routing for a semiconductor device to be disposed in the cavity. The resin compound fills in spaces between the metal leads and surrounds the cavity and provides a dielectric platform for a re-distribution layer or a build-up circuitry optionally deposited thereon.

Abstract: A wiring board includes an electrical isolator or an interconnect element incorporated with a core substrate or metal leads and a bridging element straddling over interfaces between two adjoined surfaces to electrically connect a routing circuitry on the electrical isolator or on the interconnect element to another routing circuitry on the core substrate or to the metal leads. As the bridging element offers a reliable connecting channel without direct attachment to the interfaces, any cracking or delamination across the interfaces will not affect the routing integrity.

Abstract: A face-to-face semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, the semiconductor device is face-to-face electrically coupled to another semiconductor device through a buildup circuitry therebetween.

Abstract: A method of making a wiring board having an electrical isolator and metal posts incorporated in a resin core is characterized by the provision of moisture inhibiting caps covering interfaces between the electrical isolator/metal posts and a surrounding plastic material. In a preferred embodiment, the electrical isolator and metal posts are bonded to the resin core by an adhesive substantially coplanar with the metal films on the electrical isolator, the metal posts and the metal layers on two opposite sides of the resin core at smoothed lapped top and bottom surfaces so that a metal bridge can be deposited on the adhesive at the smoothed lapped bottom surface to completely cover interfaces between the electrical isolator/metal posts and the surrounding plastic material. Conductive traces are also deposited on the smoothed lapped top surface to provide electrical contacts for chip connection and electrically coupled to the metal posts.

Abstract: The wiring board mainly includes a heat dissipation slug, core substrate and a modified binding matrix. The modified binding matrix provides mechanical bonds between the heat dissipation slug and the core substrate disposed about the peripheral sidewall of the heat dissipation slug. The modified binding matrix contains low CTE modulators dispensed in a resin adhesive to alleviate resin internal expansion and shrinkage, thereby significantly reducing the risk of the resin cracking.

Abstract: A wiring board includes a low CTE (coefficient of thermal expansion) and high thermal conductivity isolator incorporated in a resin laminate by an adhesive and a bridging element disposed over the isolator and the resin laminate and electrically coupled to a first routing circuitry on the isolator and a second routing circuitry on the resin laminate. The isolator provides CTE-compensated contact interface for a semiconductor chip to be assembled thereon, and also provides primary heat conduction for the chip. The bridging element offers a reliable connecting channel for interconnecting contact pads on the isolator to terminal pads on the resin laminate.

Abstract: A semiconductor assembly includes an encapsulated device and a thermally enhanced device face-to-face mounted together through first and second routing circuitries and a heat spreader that provides thermal dissipation and electromagnetic shielding. The encapsulated device has a first semiconductor chip sealed in an encapsulant, whereas the thermally enhanced device has a second semiconductor chip thermally conductible to a shielding lid of the heat spreader and laterally surrounded by posts of the heat spreader. The first and second semiconductor chips are mounted on two opposite sides of the first routing circuitry, and the second routing circuitry is disposed on the shielding lid and electrically coupled to the first routing circuitry by bumps. The first and second routing circuitries provide staged fan-out routing for the first and second semiconductor chips.