Abstract: A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

Abstract: A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

Abstract: A high voltage PMOS transistor 7 has improved on resistance by adjusting impurity concentration in a lightly doped drift region rim 48 to compensate for impurity segregation which occurs during the growth phase of a thick field oxide 43. During fabrication of high voltage PMOS device 7, a shallow vertical junction 230 formed by impurity segregation into field oxide 43. Implanting an HV drift region p-tank rim adjustment 220 and annealing it forms a lateral junction 250 and isolates the shallow junction 230 under field oxide 43. Thereby, the on-resistance of high voltage PMOS transistor 7 is minimized.

Abstract: An integrated circuit containing high voltage PMOS and/or NMOS devices as well as low voltage PMOS and/or NMOS devices and a simple low cost method for making same that is adaptable to many types of semiconductor processes; furthermore, the breakdown voltage of the high voltage devices is easily adjusted so that the value of R.sub.on can be optimized. High voltage MOS devices 6 and 7 are formed on substrate 10 using essentially the same process steps as are used to form low voltage MOS devices 8 and 9. Low values of R.sub.on are obtained by selecting impurity concentration levels for HV drift region n-tank 21 and for HV drift region p-tank 41 so that the depletion region distance D1 bounded by equipotential lines 301a and 301j and the depletion region distance D1a bounded by equipotential lines 401a and 401h are smaller than the physical size D2 and D2a of drift regions 41 and 21, respectively.

Abstract: An integrated circuit containing high voltage PMOS and/or NMOS devices as well as low voltage PMOS and/or NMOS devices and a simple low cost method for making same that is adaptable to many types of semiconductor processes; furthermore, the breakdown voltage of the high voltage devices is easily adjusted so that the value of R.sub.on can be optimized. High voltage MOS devices 6 and 7 are formed on substrate 10 using essentially the same process steps as are used to form low voltage MOS devices 8 and 9. Low values of R.sub.on are obtained by selecting impurity concentration levels for HV drift region n-tank 21 and for HV drift region p-tank 41 so that the depletion region distance D1 bounded by equipotential lines 301a and 301j and the depletion region distance D1a bounded by equipotential lines 401a and 401h are smaller than the physical size D2 and D2a of drift regions 41 and 21, respectively.