Patents by Inventor Chia-En CHEN

Chia-En CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240188130
    Abstract: Techniques pertaining to anti-motion and anti-interference frame exchange sequences in wireless communications are described. A station (STA), such as a Wi-Fi equipment, determines to enable a frame exchange sequence (FES). The STA then communicates with one or more other STAs by utilizing the FES in which preamble puncturing sounding and data transmission are performed in a same transmission opportunity (TXOP).
    Type: Application
    Filed: October 4, 2023
    Publication date: June 6, 2024
    Inventors: Li-Chieh Chen, Kuo-Wei Chen, Chia-Jung Hsu, Yi-Hsuan Chung, Ming-Hsiang Tseng, Wei-Hsu Chen, Cheng-En Hsieh
  • Patent number: 11997843
    Abstract: A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Chia-En Huang, Yen-Huei Chen, Yih Wang
  • Publication number: 20240170341
    Abstract: Semiconductor devices and methods of manufacture are discussed. In an embodiment, a method of manufacturing a semiconductor device includes: forming first nanostructures from a first material over a substrate; forming second nanostructures from a second material different from the first material over the substrate, wherein the first nanostructures and the second nanostructures alternate vertically above the substrate; removing the first nanostructures; after the removing the first nanostructures forming an interposer in between the second nanostructures; after the forming the interposer forming a first source/drain region over the substrate and in direct physical contact with the second nanostructures; and removing the interposer exposing surfaces of each of the second nanostructures.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 23, 2024
    Inventors: Yu-Ming Chen, Tsung-Lin Lee, Chia-Ho Chu, Sung-En Lin, Sen-Hong Syue
  • Patent number: 11963348
    Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Publication number: 20240098016
    Abstract: A method for performing adaptive multi-link aggregation dispatching control in multi-link operation architecture and associated apparatus are provided.
    Type: Application
    Filed: June 19, 2023
    Publication date: March 21, 2024
    Applicant: MEDIATEK INC.
    Inventors: Kuo-Wei Chen, Chia-Shun Wan, Cheng-En Hsieh, Po-Chi Chen
  • Patent number: 10589168
    Abstract: A fluid film game toy includes a racket including an open frame, a handle connected to the outer perimeter of the open frame and a film-forming face located on the inner perimeter of the open frame for creating a fluid film within the open frame, and a game component to be placed on the fluid film and moved on the fluid film by the player who manipulates the handle to move and/or tilt the open frame.
    Type: Grant
    Filed: September 9, 2018
    Date of Patent: March 17, 2020
    Assignee: HOLD ENTERPRISE CO., LTD.
    Inventors: Shau-Chi Lin, Chia-En Chen
  • Publication number: 20200078664
    Abstract: A fluid film game toyu includes a racket including an open frame, a handle connected to the outer perimeter of the open frame and a film-forming face located on the inner perimeter of the open frame for creating a fluid film within the open frame, and a game component to be placed on the fluid film and moved on the fluid film by the player who manipulates the handle to move and/or tilt the open frame.
    Type: Application
    Filed: September 9, 2018
    Publication date: March 12, 2020
    Inventors: Shau-Chi LIN, Chia-En CHEN