Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.

Abstract: The invention discloses a stereo enhancement system and a stereo enhancement method. The stereo enhancement system includes a beamforming unit and a signal processing unit. The beamforming unit is used for receiving a plurality of input sound signals and generating a plurality of beamforming sound signals corresponding to a plurality of direction intervals respectively. The signal processing unit is coupled to the beamforming unit and used for receiving the plurality of beamforming sound signals corresponding to the plurality of direction intervals respectively and generating a first synthesized output sound signal and a second synthesized sound signal accordingly.

Abstract: A light module includes a light guide plate, a first light source and a second light source. The light guide plate has an inner light emitting surface, an outer light emitting surface opposite to the inner light emitting surface, and a light incident surface connecting the inner light emitting surface and the outer light emitting surface. The first light source is disposed on the light incident surface and located between the inner light emitting surface and the outer light emitting surface, and the first light source emits light of a first color temperature. The second light source is disposed on the light incident surface and located between the first light source and the inner light emitting surface, and the second light source emits light of a second color temperature, and the difference between the first color temperature and the second color temperature is greater than 2000K.

Abstract: An electronic device including a die and a connection structure electrically connected to the die is disclosed. The connection structure includes a first insulating layer including an opening, a second insulating layer, a first metal element disposed between the first insulating layer and the second insulating layer, a second metal element disposed in the opening and electrically connected to the first metal element, and a conductive element. The second metal element is electrically connected between the conductive element and the first metal element. A first surface and a second surface of the first insulating layer are contacted with the first metal element and the conductive element respectively. The first insulating layer includes first filling elements, the second insulating layer includes second filling elements, and in a cross-sectional view, a second maximum size of the second filling elements is greater than a first maximum size of the first filling elements.

Abstract: The invention provides an anti-allergic peptide and a use thereof for immune regulation and anti-allergy, the anti-allergic peptide is capable of inhibiting secretion of cytokines related to allergic reactions and regulating allergic reactions, and the anti-allergic peptide comprises an amino acid sequence shown in SEQ ID No: 1, SEQ ID No: 2, SEQ ID No: 3, SEQ ID No: 4 or SEQ ID No: 5, or a homologous amino acid sequence derived from substitution, deletion, and addition of one amino acid or more than one amino acid of any of the above sequences.

Abstract: An online system receives information describing an order placed by a user of the online system and a set of contextual features associated with servicing the order. The online system also retrieves a set of user features associated with the user. The online system accesses a machine learning model trained to predict a tip amount the user is likely to provide for servicing the order and applies the machine learning model to a set of inputs, in which the set of inputs includes the information describing the order, the set of user features, and the set of contextual features. The online system then determines a suggested tip amount for servicing the order based on the predicted tip amount.

Abstract: An electronic device is provided. The electronic device includes at least one electrical connection structure. The at least one electrical connection structure includes a first substrate, a first conductive pad, a second substrate, a second conductive pad, a through hole, and a conductive material. The first conductive pad is disposed on the first substrate. The first conductive pad includes at least two sub-parts, and the at least two sub-parts respectively include a first upper surface. The second conductive pad is disposed on the second substrate. The second conductive pad includes a second upper surface. The through hole passes through the first substrate and exposes a portion of the second upper surface. Furthermore, the conductive material is partially disposed in the through hole and in contact with at least one first upper surface and the second upper surface.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

Abstract: A display apparatus is provided. The display apparatus includes a substrate, a transistor, a metal layer, and a light-emitting diode. The transistor is disposed on the substrate. The metal layer is disposed on the transistor and electrically connected to the transistor, wherein a first distance is between the upper surface of the metal layer and the substrate in a direction perpendicular to the substrate. The light-emitting diode is disposed on the metal layer, wherein the light-emitting diode includes a light-emitting diode body and an electrode, the light-emitting diode body is electrically connected to the metal layer via the electrode, the light-emitting diode body has a first surface and a second surface opposite to the first surface, the first surface and the second surface are parallel to the substrate, and in the direction above, a second distance is between the first surface and the second surface, wherein the ratio of the second distance to the first distance is greater than or equal to 0.

Abstract: An electronic device is provided. The electronic device includes at least one electrical connection structure. The at least one electrical connection structure includes a first substrate, a first conductive pad, a second substrate, a second conductive pad, a through hole and a conductive material. The first conductive pad is disposed on the first substrate. The first conductive pad includes a first upper surface and a first side surface. The second substrate is disposed opposite to the first substrate. The second conductive pad is disposed on the second substrate. The second conductive pad includes a second upper surface. The through hole penetrates through the first substrate. In addition, in a top-view diagram, the through hole includes an extension area. The conductive material is partially disposed in the extension area and in contact with the first upper surface and the second upper surface.

Abstract: A sole data collection device and a sole data collection method are disclosed. The sole data collection device includes an image capture module, a temperature detection module and a monofilament testing module. The sole data collection device is used for collecting the sole data of a user, and the sole data is transmitted to a cloud server. The sole data collection device and the sole data collection method are not only convenient for a user to collect sole data at home at any time, but also allow the user's caregiver and/or relevant medical care personnel to extract the sole data from the cloud server to screen the user's plantar condition, so as to solve the problem that it is time-consuming and costly to go to a medical institution for relevant examinations.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A display device includes a reflective display panel, a light guide plate, a light source, and a first optical adhesive layer. The light guide plate is located on the reflective display device. The light guide plate has a top surface, a bottom surface and a light incident surface connecting the top surface and the bottom surface. The light guide plate further includes multiple microstructures located on the top surface and multiple lenticular structures located on the bottom surface. The light source faces the light incident surface of the light guide plate. The first optical adhesive layer is located below the light guide plate and in contact with the lenticular structure. A refractive index of the first optical adhesive layer is lower than a refractive index of the light guide plate.

Abstract: Aspects of the disclosure provide a method and an apparatus for executing a program, e.g., a neural network (NN) inference. For example, the apparatus can include an executor and a dynamic loading agent. The executor can be coupled to a second memory, and be configured to execute a portion of the NN inference loaded on the second memory from a first memory that stores the NN inference, and to generate a signal based on a progress of the execution of the NN inference. The dynamic loading agent can be coupled to the executor, the first memory and the second memory, and be configured to load a next portion of the NN inference stored in the first memory to the second memory and to manage power supplied to the first memory based on the signal from the executor and an inference executing scheme stored in the second memory.

Abstract: A wireless device is configured to select a beam and/or an antenna based on detection a detected position and/or orientation of the device relative to a remote device. The device obtains motion data indicating a change in position or orientation of the wireless device. The device determines its pose relative to the remote device. The device accesses a coverage map that associates, for each potential pose for the device with respect to the remote device: an antenna for communicating with the remote device and/or a beam for communicating with the remote device. The device selects a particular antenna and/or a particular beam for communicating with the remote device; and causes transmission or reception of data to or from the remote device by the particular antenna and/or the particular beam.