Abstract: A method for identifying an object, an optical sensing apparatus and a system are provided. A controller of the system drives multiple light sources of the optical sensing apparatus to emit the multiple light beams with different beam angles, controls a light sensor to sense the lights reflected by the object, and performs the method for identifying the object. In the method, the light sensor is used to sense a first light emitted by a first light source with a first beam angle reflected by the object, and sense an intensity of the reflected first light. The light sensor is also used to sense a second light emitted by a second light source with a second beam angle reflected by the object and sense another intensity of the reflected second light. Therefore, the object can be identified by integrating information of the intensities obtained by the light sensor.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A use of a Crassocephalum rabens extract in detoxification is disclosed. The Crassocephalum rabens extract has the activity to remove such substances in an organism or the cells thereof as a heavy metal, so the administration of an effective amount of the Crassocephalum rabens extract or of a composition containing the Crassocephalum rabens extract to an individual can effectively reduce the heavy metal content in the individual's body and help restore the individual's liver functions.

Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

Abstract: This invention provides a high-efficient single-cell collection method using a specially designed collection well and collection pipet tip for particle/cell collection from the collection well. The structures of the collection well and pipet tip eliminate fluidic dead volume in the collection, resulting in all (or most) of the particles/cells can be brought into the collection pipette tip with the flow. The advantages of this invention in cell manipulation include high cell collection efficiency, low cell damage and easy operation procedure.

Abstract: An augmented reality operating procedure judgment system is provided. The augmented reality operating procedure judgment system includes an augmented reality device and a processor. The augmented reality device receives a plurality of real-time images. The processor accesses an inference model stored in a storage device. The processor judges a standard operating procedure (SOP) result corresponding to the plurality of real-time images through the inference model. The augmented reality device displays the standard operating procedure result on one of the plurality of real-time images. Therefore, the effect of judging whether an operator is following the standard operating procedure may be achieved.

Abstract: A lipid compound or a derivative thereof and a pharmaceutical composition employing the same are provided. The lipid compound has a structure represented by Formula (I): wherein Z1, Z2, Z3 and Z4 are as disclosed in the specification.

Abstract: A selective EMI shielding structure for a semiconductor package and a method of fabrication thereof is disclosed. The semiconductor package, comprising: a substrate having a first face; at least one first electronic component mounted adjacent to a first region of the first face; a least one second electronic component mounted adjacent to a second region of the first face; and an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the first electronic component, and wherein the encapsulant covers the second electronic component through a layer of conductive material.

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

Abstract: A decorative flexible-electronic-film structure includes a mechanical member and a flexible electronic molded film. The mechanical member includes a mainboard part and a curved clamping part, and an accommodating slot is formed on the mainboard part. The flexible electronic molded film includes a body part, a side hook part and an electronic component, an inner surface of the body part faces the mainboard part, the electronic component is disposed on the inner surface and corresponds to the accommodating slot, and the side hook part is formed on the periphery of the body part and is curved. The flexible electronic molded film is assembled onto the mechanical member, with the body part overlapping the mainboard part, the electronic component being accommodated in the accommodating slot, and the side hook part being buckled to the clamping part. A method of forming the decorative flexible-electronic-film structure is also provided.

Abstract: A method of manufacturing a capacitor including the operations of etching a plurality of primary trenches into a first region of a substrate, the primary trenches extending in a first direction, etching a plurality of secondary trenches into the first region of the substrate, the secondary trenches extending in a second direction other than the first direction, with the adjacent secondary trenches and adjacent primary trenches jointly defining an island structure having an upper surface that is recessed relative to an upper surface a surrounding substrate, and depositing a series of film pairs including a dielectric layer and a conductive layer.

Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

Abstract: A photomask structure including a first layout pattern and a second layout pattern is provided. The second layout pattern is located on one side of the first layout pattern. The first layout pattern and the second layout pattern are separated from each other. The first layout pattern has a first edge and a second edge opposite to each other. The second layout pattern has a third edge and a fourth edge opposite to each other. The third edge of the second layout pattern is adjacent to the first edge of the first layout pattern. The second layout pattern includes a first extension portion exceeding an end of the first layout pattern. The first extension portion includes a first protruding portion protruding from the third edge of the second layout pattern. The first protruding portion exceeds the first edge of the first layout pattern.

Abstract: An electronic switch device and an electronic switch system are provided, wherein the electronic switch system includes: an electronic switch device, which includes: a sensing module, which includes: a pressure sensing module for providing a pressure sensing signal; and a touch control sensing module disposed on the pressure sensing module for providing a touch control sensing signal; and a comparator circuit coupled to the sensing module for receiving the pressure sensing signal.

Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.