Patents by Inventor Chia-Feng CHEN
Chia-Feng CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955389Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.Type: GrantFiled: July 27, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
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Patent number: 11937932Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.Type: GrantFiled: July 8, 2022Date of Patent: March 26, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITYInventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
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Patent number: 11936299Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.Type: GrantFiled: September 21, 2020Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chu Fu Chen, Chi-Feng Huang, Chia-Chung Chen, Chin-Lung Chen, Victor Chiang Liang, Chia-Cheng Pao
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Publication number: 20240088224Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
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Publication number: 20240071954Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240071953Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Patent number: 9778408Abstract: A backlight module includes a plurality of first light emitting elements and a light guiding plate including a first side, a second side and a light output side having microstructures at least disposed in a near-light region of the light guiding plate. The near-light region is defined as from a first line to a predetermined second line at the light output side. The microstructure has a width P and height H, the light-guiding plate has a thickness T, a pitch between the adjacent first light-emitting elements is defined as PLED, a projection distance from a luminance measuring line of the backlight module to the first light-emitting elements is defined as A. Under the conditions 0<A?120 mm, 0<[(H/P)/T]*PLED?15 and 0<luminance variation?100%, the structure characteristic of the backlight module is bounded by a first equation: A=0.2{[(H/P)/T]*PLED}2?2{[(H/P)/T]*PLED}+105 mm and a second equation: A=0.2{[(H/P)/T]*PLED}2?2{[(H/P)/T]*PLED}+0.1 mm.Type: GrantFiled: May 14, 2014Date of Patent: October 3, 2017Assignee: Innolux CorporationInventors: Chi-Liang Chang, Chia-Wei Hu, Yen-Liang Chen, Chia-Feng Chen
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Publication number: 20160298006Abstract: An optical adhesive composition is provided. The optical adhesive composition includes an acrylic-based polymer having at least one group selected from hydroxyl, amino and carboxylic acid group, a crosslinking agent having isocyanate groups, a acrylic-based oligomer having at least one unsaturated group and a photo initiator, wherein based on 100 parts by weight of the acrylic-based polymer, the content of the acrylic-based oligomer is 1 part by weight to 7 parts by weight.Type: ApplicationFiled: June 3, 2015Publication date: October 13, 2016Applicant: KOATECH TECHNOLOGY CORPORATIONInventors: Kuo-Teng Hsu, Chih-Tsung Lu, Tse-Hung Hsiao, Yi-Chang Lin, Chia-Feng Chen, Lie-Zen Chung
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Publication number: 20150370122Abstract: A display including a backlight module, a liquid crystal module, and a first adhesive layer is provided. The backlight module includes a light source and a plurality of first optical films. The first optical films are stacked on the light source, and at least one first optical film has a hard-coat film layer. The liquid crystal module is disposed on the backlight module. The liquid crystal module includes a liquid crystal element, a plurality of first adhesive layers, and a plurality of second optical films. The second optical films are respectively disposed on two opposite surfaces of the liquid crystal element, wherein at least one second optical film has a hard-coat film layer. Each first adhesive layer is disposed between a second optical film and the liquid crystal element.Type: ApplicationFiled: September 24, 2014Publication date: December 24, 2015Applicant: KOATECH TECHNOLOGY CORPORATIONInventors: Kuo-Teng Hsu, Chih-Tsung Lu, Tse-Hung Hsiao, Yi-Chang Lin, Chia-Feng Chen, Lie-Zen Chung
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Publication number: 20150234103Abstract: A film structure including a substrate, a coating layer, and an adhesive layer is provided. The coating layer and the adhesive layer are respectively disposed on two opposite surfaces of the substrate. The adhesive layer includes a chemical composition for filtering a light ray. The adhesive layer cuts off the light ray in a specific wavelength range when the light ray passes through the adhesive layer. A cut-off rate of the light ray in a wavelength range of 380 nm to 420 nm is greater than 80%.Type: ApplicationFiled: May 30, 2014Publication date: August 20, 2015Applicant: KOATECH TECHNOLOGY CORPORATIONInventors: Kuo-Teng Hsu, Chih-Tsung Lu, Tse-Hung Hsiao, Yi-Chang Lin, Chia-Feng Chen, Lie-Zen Chung
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Publication number: 20140340936Abstract: A backlight module includes a plurality of first light emitting elements and a light guiding plate including a first side, a second side and a light output side having microstructures at least disposed in a near-light region of the light guiding plate. The near-light region is defined as from a first line to a predetermined second line at the light output side. The microstructure has a width P and height H, the light-guiding plate has a thickness T, a pitch between the adjacent first light-emitting elements is defined as PLED, a projection distance from a luminance measuring line of the backlight module to the first light-emitting elements is defined as A. Under the conditions 0<A?120 mm, 0<[(H/P)/T]*PLED?15 and 0<luminance variation?100%, the structure characteristic of the backlight module is bounded by a first equation: A=0.2{[(H/P)/T]*PLED}2?2{[(H/P)/T]*PLED}+105 mm and a second equation: A=0.2{[(H/P)/T]*PLED}2?2{[(H/P)/T]*PLED}+0.1 mm.Type: ApplicationFiled: May 14, 2014Publication date: November 20, 2014Applicant: InnoLux CorporationInventors: Chi-Liang CHANG, Chia-Wei HU, Yen-Liang CHEN, Chia-Feng CHEN