Abstract: A polypeptide and a use thereof in regulating blood glucose level and/or reducing fat are disclosed. The amino acid sequence of the polypeptide includes the sequence of SEQ ID No.: 1, the sequence of SEQ ID No.: 2, the sequence of SEQ ID No.: 3, the sequence of SEQ ID No.: 4, or a sequence obtained by modifying at least one amino acid in any of the aforesaid sequences. The polypeptide disclosed herein has the physiological activity to enhance fat metabolism and regulate blood glucose level. Therefore, administering an effective amount of the polypeptide, or a composition containing the polypeptide, to an individual can effectively produce the effect of treating or preventing a disease related to blood glucose imbalance or to imbalance in fat metabolism.

Abstract: The invention discloses a stereo enhancement system and a stereo enhancement method. The stereo enhancement system includes a beamforming unit and a signal processing unit. The beamforming unit is used for receiving a plurality of input sound signals and generating a plurality of beamforming sound signals corresponding to a plurality of direction intervals respectively. The signal processing unit is coupled to the beamforming unit and used for receiving the plurality of beamforming sound signals corresponding to the plurality of direction intervals respectively and generating a first synthesized output sound signal and a second synthesized sound signal accordingly.

Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: The invention provides an anti-allergic peptide and a use thereof for immune regulation and anti-allergy, the anti-allergic peptide is capable of inhibiting secretion of cytokines related to allergic reactions and regulating allergic reactions, and the anti-allergic peptide comprises an amino acid sequence shown in SEQ ID No: 1, SEQ ID No: 2, SEQ ID No: 3, SEQ ID No: 4 or SEQ ID No: 5, or a homologous amino acid sequence derived from substitution, deletion, and addition of one amino acid or more than one amino acid of any of the above sequences.

Abstract: An electronic device is provided. The electronic device includes at least one electrical connection structure. The at least one electrical connection structure includes a first substrate, a first conductive pad, a second substrate, a second conductive pad, a through hole, and a conductive material. The first conductive pad is disposed on the first substrate. The first conductive pad includes at least two sub-parts, and the at least two sub-parts respectively include a first upper surface. The second conductive pad is disposed on the second substrate. The second conductive pad includes a second upper surface. The through hole passes through the first substrate and exposes a portion of the second upper surface. Furthermore, the conductive material is partially disposed in the through hole and in contact with at least one first upper surface and the second upper surface.

Abstract: An electronic device is provided. The electronic device includes at least one electrical connection structure. The at least one electrical connection structure includes a first substrate, a first conductive pad, a second substrate, a second conductive pad, a through hole and a conductive material. The first conductive pad is disposed on the first substrate. The first conductive pad includes a first upper surface and a first side surface. The second substrate is disposed opposite to the first substrate. The second conductive pad is disposed on the second substrate. The second conductive pad includes a second upper surface. The through hole penetrates through the first substrate. In addition, in a top-view diagram, the through hole includes an extension area. The conductive material is partially disposed in the extension area and in contact with the first upper surface and the second upper surface.

Abstract: A sole data collection device and a sole data collection method are disclosed. The sole data collection device includes an image capture module, a temperature detection module and a monofilament testing module. The sole data collection device is used for collecting the sole data of a user, and the sole data is transmitted to a cloud server. The sole data collection device and the sole data collection method are not only convenient for a user to collect sole data at home at any time, but also allow the user's caregiver and/or relevant medical care personnel to extract the sole data from the cloud server to screen the user's plantar condition, so as to solve the problem that it is time-consuming and costly to go to a medical institution for relevant examinations.

Abstract: Aspects of the disclosure provide a method and an apparatus for executing a program, e.g., a neural network (NN) inference. For example, the apparatus can include an executor and a dynamic loading agent. The executor can be coupled to a second memory, and be configured to execute a portion of the NN inference loaded on the second memory from a first memory that stores the NN inference, and to generate a signal based on a progress of the execution of the NN inference. The dynamic loading agent can be coupled to the executor, the first memory and the second memory, and be configured to load a next portion of the NN inference stored in the first memory to the second memory and to manage power supplied to the first memory based on the signal from the executor and an inference executing scheme stored in the second memory.

Abstract: A selective EMI shielding structure for a semiconductor package and a method of fabrication thereof is disclosed. The semiconductor package, comprising: a substrate having a first face; at least one first electronic component mounted adjacent to a first region of the first face; a least one second electronic component mounted adjacent to a second region of the first face; and an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the first electronic component, and wherein the encapsulant covers the second electronic component through a layer of conductive material.

Abstract: Aspects of the disclosure provide an apparatus for executing a program that involves a plurality of operators. For example, the apparatus can include an executor and an analyzer. The executor can be configured to execute the program with at least a first one of the operators loaded on a second memory from a first memory that stores the operators and to generate a signal based on a progress of the execution of the program with the first operator. The analyzer can be coupled to the executor, the first memory and the second memory, and configured to load at least a second one of the operators of the program next to the first operator stored in the first memory to the second memory before the executor finishes execution of the program with the first operator based on the signal from the executor and an executing scheme stored in the second memory.

Abstract: A selective EMI shielding structure for a semiconductor package and a method of fabrication thereof is disclosed. The semiconductor package, comprising: a substrate having a first face; at least one first electronic component mounted adjacent to a first region of the first face; a least one second electronic component mounted adjacent to a second region of the first face; and an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the first electronic component, and wherein the encapsulant covers the second electronic component through a layer of conductive material.

Abstract: Aspects of the disclosure provide an apparatus for executing a program that involves a plurality of operators. For example, the apparatus can include an executor and an analyzer. The executor can be configured to execute the program with at least a first one of the operators loaded on a second memory from a first memory that stores the operators and to generate a signal based on a progress of the execution of the program with the first operator. The analyzer can be coupled to the executor, the first memory and the second memory, and configured to load at least a second one of the operators of the program next to the first operator stored in the first memory to the second memory before the executor finishes execution of the program with the first operator based on the signal from the executor and an executing scheme stored in the second memory.

Abstract: Aspects of the disclosure provide a method and an apparatus for executing a program, e.g., a neural network (NN) inference. For example, the apparatus can include an executor and a dynamic loading agent. The executor can be coupled to a second memory, and be configured to execute a portion of the NN inference loaded on the second memory from a first memory that stores the NN inference, and to generate a signal based on a progress of the execution of the NN inference. The dynamic loading agent can be coupled to the executor, the first memory and the second memory, and be configured to load a next portion of the NN inference stored in the first memory to the second memory and to manage power supplied to the first memory based on the signal from the executor and an inference executing scheme stored in the second memory.