Patents by Inventor Chia-Fu Lin

Chia-Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8497584
    Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: July 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
  • Patent number: 7906425
    Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: March 15, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
  • Patent number: 7468321
    Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: December 23, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Ming Ching, Chia-Fu Lin, Wen-Hsiang Tseng, Ta-Min Lin, Yen-Ming Chen, Hsin-Hui Lee, Chao-Yuan Su, Wen-Hsiang Tseng
  • Patent number: 7276454
    Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.
    Type: Grant
    Filed: November 2, 2002
    Date of Patent: October 2, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Ming Ching, Chia Fu Lin, Wen-Hsiang Tseng, Ta-Min Lin, Yen-Ming Chen, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
  • Publication number: 20070028445
    Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
    Type: Application
    Filed: October 13, 2006
    Publication date: February 8, 2007
    Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
  • Patent number: 7134199
    Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: November 14, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
  • Patent number: 6974659
    Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: December 13, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
  • Patent number: 6918397
    Abstract: A flush system comprising a network of conduits, valves and screens that can be interposed between the process container and solvent re-claim tank components of a dry film photoresist (DFR) remover system, for example, that is used in the processing and packaging of integrated circuit chips. By operation of the valves in the flush system, DFR particles can be removed from the DFR remover system in order to prevent or minimize particle clogging of a particle filter in the DFR remover system. The screens in the flush system can be periodically cleaned by reverse flow of solvent or by operation of a nitrogen and DI (deionized) water purge system.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: July 19, 2005
    Assignee: Taiwan Semiconductor
    Inventors: Ta-Min Lin, Szu-Yao Wang, Chia-Fu Lin, Kai-Ming Ching, Wen-Hsiang Tseng
  • Patent number: 6805279
    Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4, SF4, and H2 and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: October 19, 2004
    Assignee: Taiwan SEmiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yeng-Ming Chen, Kai-Ming Chin, Li-Chi Chen, Hao-Chih Tien
  • Patent number: 6802250
    Abstract: A stencil design for solder paste printing, or other metal stencil printing, is disclosed. A stencil for stencil printing of solder onto a semiconductor wafer for semiconductor wafer bumping includes a substrate. The substrate has a hole defined therein substantially shaped to correspond to and receptive to the semiconductor wafer. An interior edge of the substrate surrounds the hole, and has an upper lip under which the semiconductor wafer is positioned. The upper lip of the interior edge of the substrate surrounding the hole substantially prevents the solder from flowing onto sides and a bottom of the semiconductor wafer during stencil printing of the solder. The cross-profile shape of the upper lip may in one embodiment be rectangular, whereas in another embodiment be triangular.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: October 12, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
  • Patent number: 6797075
    Abstract: A Ferris wheel-like stripping or cleaning mechanism that can be used in semiconductor fabrication, such as in photoresist or other stripping, or wafer or other cleaning, is disclosed. A stripping mechanism can include a container to hold a chemical, such as a photoresist stripping chemical, a wafer cleaning chemical, or another type of chemical. The mechanism can also include a component to move semiconductor wafers through the chemical in the container in a Ferris wheel-like motion. The component may include wafer holders for the wafers that are swivably mounted about an axis of rotation. As the one or more wafer holders rotate about the axis of rotation through the chemical in the container, the wafer holders remain in a substantially constant vertical and horizontal orientation.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: September 28, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Ming Ching, Chia-Fu Lin, Wen-Hsiang Tseng, Ta-Min Lin, Yen-Ming Chen, Hsin-Hui Lee
  • Publication number: 20040180296
    Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.
    Type: Application
    Filed: March 26, 2004
    Publication date: September 16, 2004
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
  • Patent number: 6765277
    Abstract: Within a method for fabricating a microelectronic, and a microelectronic fabrication fabricated in accord with the method, there is formed upon a bond pad formed over a substrate a conductor passivation layer. Within the method and the microelectronic fabrication, the bond pad is formed from a conductor material selected from the group consisting of aluminum and aluminum alloy conductor materials, and the conductor passivation layer is formed from a noble metal conductor material. The invention provides particular value for fabricating color filter sensor image array optoelectronic microelectronic fabrications with attenuated bond pad corrosion.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: July 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Chen, Chia-Fu Lin, Yang-Tung Fan, Hong-Wen Huang, Cheng-Yu Chu
  • Patent number: 6756294
    Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the Created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: June 29, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
  • Patent number: 6743660
    Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.
    Type: Grant
    Filed: January 12, 2002
    Date of Patent: June 1, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
  • Publication number: 20040087175
    Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.
    Type: Application
    Filed: November 2, 2002
    Publication date: May 6, 2004
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Kai-Ming Ching, Chia Fu Lin, Wen-Hsiang Tseng, Ta-Min Lin, Yen-Ming Chen, Hsin-Hui Lee, Chao-Yuan Su, Wen-Hsiang Tseng
  • Patent number: 6715524
    Abstract: A DFR laminating and PET removing system which is capable of both laminating a dry film resist (DFR) layer on a semiconductor wafer and removing a DFR support film such as polyethylene terepthalate (PET) from the DFR layer on the wafer at a single location. The DFR laminating and PET removing system of the present invention comprises a PET support film removing head for removing a portion of PET film from the semiconductor wafer substrate after the PET film portion and dry film resist (DFR) portion are laminated from a DFR tape onto the wafer and before the DFR portion is cut from the DFR tape.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: April 6, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Chen Chen, Chia-Tsun Hsu, Chia-Fu Lin, Kuo-Ching Lee, Yen-Ming Chen, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su
  • Patent number: 6712260
    Abstract: A method of forming reflowed bumps comprising the following sequential steps. A wafer is provided. A series of spaced initial bumps is formed upon the wafer. The initial bumps having exposed side walls and top surfaces and organic residue over the initial bump side walls and/or the initial bump top surfaces. The organic residue is simultaneously removed from the initial bump side walls and top surfaces with the forming a surface oxide layer over the initial bump side walls and top surfaces. The surface oxide layer is stripped from the initial bump top surfaces and an upper portion of the initial bump side walls to form partially exposed bumps. The partially exposed bumps are heat treated to melt the partially exposed bumps to form the reflowed bumps.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: March 30, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Wen-Chang Kuo, Chia-Fu Lin, Sheng-Liang Pan, Szu-Yao Wang, Cheng-Yu Chu
  • Publication number: 20040000580
    Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4, SF4, and H2 and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 1, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yeng-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Hao-Chih Tien
  • Publication number: 20030229986
    Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 18, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian