Patents by Inventor Chia-Fu Tsai

Chia-Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240157217
    Abstract: A golf teaching method and a golf teaching system are provided. The golf teaching method includes: configuring image capturing devices and golf simulator to capture swing images and corresponding simulator data records, when a user performs a golf swing; configuring an expert model that includes expert motion information and corresponding correction suggestion information; configuring a computing device to perform an analysis process on the swing images and the simulator data records to divide the golf swing into user motions according to stages and obtaining records of user motion information corresponding to the plurality of stages, and to compare the user motion information with the corresponding expert motion information in each stage through the expert model, and to provide the corresponding correction suggestion information according to a comparison result; and configuring a user interface to provide the correction suggestion information.
    Type: Application
    Filed: April 20, 2023
    Publication date: May 16, 2024
    Inventors: CHENG-HUNG TSAI, CHIA-YU JIH, CHIH-CHUNG CHIEN, LI-LIN LU, SHAO-JUN TAN, WEN-FU LAI
  • Publication number: 20240120735
    Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: Chia-Lin HSU, Ming-Fu TSAI, Yu-Ti SU, Kuo-Ji CHEN
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 7001098
    Abstract: A lock structure. The lock structure includes a first element, a second element, a guiding element and a fixing pin. The first element has a guide hole and a first through hole located under the guide hole. The second element is deposed under the first element and has a second through hole that is co-axially aligned with the first through hole. The guiding element rotates and is movably disposed in the guide hole. The guiding element has a third through hole aligned with the first through hole. The fixing pin is inserted through the third through hole, guide hole, first through hole and second through hole and has a first retaining portion. The first retaining portion is formed on the lower portion of the fixing pin and located under the second element.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: February 21, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Cheng Lin, Jung-Huang Peng, Chin-Chen Chang, Chia-Fu Tsai, Zhen-Dao Shen
  • Publication number: 20040258473
    Abstract: A lock structure. The lock structure includes a first element, a second element, a guiding element and a fixing pin. The first element has a guide hole and a first through hole located under the guide hole. The second element is deposed under the first element and has a second through hole that is co-axially aligned with the first through hole. The guiding element rotates and is movably disposed in the guide hole. The guiding element has a third through hole aligned with the first through hole. The fixing pin is inserted through the third through hole, guide hole, first through hole and second through hole and has a first retaining portion. The first retaining portion is formed on the lower portion of the fixing pin and located under the second element.
    Type: Application
    Filed: June 20, 2003
    Publication date: December 23, 2004
    Inventors: Hsueh-Cheng Lin, Jung-Huang Peng, Chin-Chen Chang, Chia-Fu Tsai, Zhen-Dao Shen
  • Patent number: 6732442
    Abstract: An apparatus and method for adjusting the position of a load port utilized in a semiconductor wafer processing system. Generally, a door opener can be configured for opening a door through which a semiconductor wafer may enter for subsequent positioning and processing thereof by a semiconductor wafer processing system. A load port is associated with the door opener. A calibration mechanism can then be utilized for calibrating the load port for leveling and height positioning, such that a plurality of directional axis associated with the load port do not interfere with one another, thereby conserving calibration time while permitting a single individual to perform calibration operations thereof.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: May 11, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yaw-Wen Wu, Tung-Gan Cheng, Tung-Liang Wua, Cheng-Chao Lin, Hsueh-Cheng Lin, Chia-Fu Tsai, Chih-Jung Yeh, Hung-Tse Huang, Ray-Wen Tsai
  • Publication number: 20040006883
    Abstract: An apparatus and method for adjusting the position of a load port utilized in a semiconductor wafer processing system. Generally, a door opener can be configured for opening a door through which a semiconductor wafer may enter for subsequent positioning and processing thereof by a semiconductor wafer processing system. A load port is associated with the door opener. A calibration mechanism can then be utilized for calibrating the load port for leveling and height positioning, such that a plurality of directional axis associated with the load port do not interfere with one another, thereby conserving calibration time while permitting a single individual to perform calibration operations thereof.
    Type: Application
    Filed: July 15, 2002
    Publication date: January 15, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yaw-Wen Wu, Tung-Gan Cheng, Tung-Liang Wua, Cheng-Chao Lin, Hsueh-Cheng Lin, Chia-Fu Tsai, Chih-Jung Yeh, Hung-Tse Huang, Ray-Wen Tsai
  • Patent number: 6541787
    Abstract: An apparatus and a method for aligning a loadport on a process machine are disclosed. The apparatus is constructed by a base plate, an alignment block mounted on the base plate, a light source and an optical detector. The alignment block is provided with an aperture extending longitudinally through the block, or formed in a T-shape extending both longitudinally and transversely through the block. The light source may be suitably a laser emission source, or a laser source that operates in a pulse mode. The diameter of the aperture provided in the alignment block should be sufficiently small, i.e. smaller than 5 mm, and preferably smaller than 3 mm.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: April 1, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Andrew Lin, Yi-Yu Liu, Tung-Gan Cheng, Tung-Liang Wu, Hsueh-Cheng Lin, Yaw-Wen Wu, Chia-Fu Tsai
  • Publication number: 20020155641
    Abstract: An apparatus and a method for aligning a loadport on a process machine are disclosed. The apparatus is constructed by a base plate, an alignment block mounted on the base plate, a light source and an optical detector. The alignment block is provided with an aperture extending longitudinally through the block, or formed in a T-shape extending both longitudinally and transversely through the block. The light source may be suitably a laser emission source, or a laser source that operates in a pulse mode. The diameter of the aperture provided in the alignment block should be sufficiently small, i.e. smaller than 5 mm, and preferably smaller than 3 mm.
    Type: Application
    Filed: April 18, 2001
    Publication date: October 24, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Andrew Lin, Yi-Yu Liu, Tung-Gan Cheng, Tung-Liang Wu, Hsueh-Cheng Lin, Yaw-Wen Wu, Chia-Fu Tsai