Abstract: A semiconductor device includes a semiconductor layer and a gate structure on the semiconductor layer. The gate structure includes a multi-stepped gate dielectric on the semiconductor layer and a gate electrode on the multi-stepped gate dielectric. The multi-stepped gate dielectric includes a first gate dielectric segment having a first thickness and a second gate dielectric segment having a second thickness that is less than the first thickness.

Abstract: A touch function setting method is provided. The method comprising: receiving a sequence parameter which includes multiple clicks, each of the clicks is corresponding to one of areas of a touch panel or screen; receiving a function parameter corresponding to the sequence parameter, the function parameter is corresponding to activate a function; and storing a group of touch function parameters, which includes the sequence parameter and the function parameter.

Abstract: A battery cell balancing control system and a battery management method thereof are disclosed. The battery cell balancing control system is used for managing a battery apparatus, wherein the battery apparatus has a plurality of battery cells. The battery cell balancing control system comprises a detection module, a battery management module, and an adjusting module. The detection module is used for executing a battery checking procedure on the plurality of battery cells to generate a detection result. The battery management module is used for determining whether the plurality of battery cells has a controlled cell according to the detection result. If the controlled cell has not been found among the plurality of battery cells, the battery management module controls the adjusting module to execute a battery cell balancing procedure until the controlled cell is found.

Abstract: A battery cell balancing control system and a battery management method thereof are disclosed. The battery cell balancing control system is used for managing a battery apparatus, wherein the battery apparatus has a plurality of battery cells. The battery cell balancing control system comprises a detection module, a battery management module, and an adjusting module. The detection module is used for executing a battery checking procedure on the plurality of battery cells to generate a detection result. The battery management module is used for determining whether the plurality of battery cells has a controlled cell according to the detection result. If the controlled cell has not been found among the plurality of battery cells, the battery management module controls the adjusting module to execute a battery cell balancing procedure until the controlled cell is found.

Abstract: A method for detecting a state of charge (SOC) of a battery is disclosed. The method includes inputting a pulse to the battery for receiving a response curve of the battery associated with the pulse inputted to the battery, determining a set of parameters for preparing a simulated curve, comparing a difference between the response curve and the simulated curve, determining whether the difference between the simulated curve and the response curve is less than a predetermined threshold before further utilizing the parameters to determine the SOC from a corresponding relationship.

Abstract: A method for detecting a state of charge (SOC) of a battery is disclosed. The method includes inputting a pulse to the battery for receiving a response curve of the battery associated with the pulse inputted to the battery, determining a set of parameters for preparing a simulated curve, comparing a difference between the response curve and the simulated curve, determining whether the difference between the simulated curve and the response curve is less than a predetermined threshold before further utilizing the parameters to determine the SOC from a corresponding relationship.

Abstract: A battery protection method is provided for preventing a main battery set from being damaged by a current from a load, and for lengthening the lifespan of the main battery set. The method includes the steps of: providing an auxiliary battery set; determining whether to recycle energy of the load, and performing a charging mode if affirmative; and transferring energy from the load to the auxiliary battery set when performing the charging mode. The method prevents the main battery set from being damaged due to charging at a high C rate, transfers possible damage due to the high current charging to the auxiliary battery set, lengthens the lifespan of the main battery set, and reduces the overall cost and difficulty of the maintenance of the main battery set by shifting the focus of the maintenance from the main battery set to the auxiliary battery set.

Abstract: A magnetic capacitor comprises a dielectric layer having a first surface and a second surface opposed to the first surface, a first electrode disposed on the first surface of the dielectric layer and a second electrode disposed on the second surface of the dielectric layer. The first electrode has a plurality of first magnetic dipoles with a same first direction, and the first direction of the first magnetic dipoles is perpendicular to the dielectric layer.

Abstract: A thin film capacitor includes a first electrode, second electrode opposite to the first electrode, and a dielectric layered structure disposed between the first and second electrodes and having a doped dielectric layer. The doped dielectric layer contains a dopant therein and has a doping concentration greater than 0 atoms/cm3 and not greater than 1010 atoms/cm3.

Abstract: A method for inspecting a pattern defect process is disclosed, in which a layer is formed to raise a signal-to-noise ratio on the substrate. This invention also provides a method for inspecting a pattern defect process. First of all, a substrate is provided. Then, a device profile is formed on the substrate, wherein the device profile comprises a defect portion. Then, a layer is formed on the device profile and the substrate, wherein the layer has an etch selectivity different from the etch selectivity of the device profile. Next, the layer is removed partially to stop on the device profile and to cause a revere mask. Then, the device profile is etched on the substrate by using the revere mask as a mask. Finally, the revere mask is removed.

Abstract: An improved post-metal-plasma-etching wafer cleaning process includes providing a wafer having a naked metal structure thereon, dipping the wafer into a first cleaning vessel having a volume of basic solution therein, and after dipping the wafer in the first cleaning vessel, the wafer is then transferred into a second cleaning vessel to perform at least one cycle of a hot QDR cleaning process.

Abstract: A method for inspecting a pattern defect process is disclosed, in which a layer is formed to raise a signal-to-noise ratio on the substrate. This invention also provides a method for inspecting a pattern defect process. First of all, a substrate is provided. Then, a device profile is formed on the substrate, wherein the device profile comprises a defect portion. Then, a layer is formed on the device profile and the substrate, wherein the layer has an etch selectivity different from the etch selectivity of the device profile. Next, the layer is removed partially to stop on the device profile and to cause a revere mask. Then, the device profile is etched on the substrate by using the revere mask as a mask. Finally, the revere mask is removed.

Abstract: In accordance with the present invention, a method is provided for dry cleaning a processing chamber. This method comprises the step of introducing a first cleaning process gas into the processing chamber. A plasma is formed from the first cleaning process gas and maintained for a first time period. Next, repeating the step of introducing the cleaning process gas, a second cleaning process gas is introduced into the processing chamber and maintained the plasma for a second time period. As a result, the present invention is capable of removing polymer built up on the processing chamber's interior surfaces to achieve a high yield and maintaining throughput of the substrates in the plasma processing system.

Abstract: In accordance with the present invention, a method is provided for dry cleaning a processing chamber. This method comprises the step of introducing a first cleaning process gas into the processing chamber. A plasma is formed from the first cleaning process gas and maintained for a first time period. Next, repeating the step of introducing the cleaning process gas, a second cleaning process gas is introduced into the processing chamber and maintained the plasma for a second time period. As a result, the present invention is capable of removing polymer built up on the processing chamber's interior surfaces to achieve a high yield and maintaining throughput of the substrates in the plasma processing system.

Abstract: A process for cleaning the interior walls of a reaction chamber after a number of silicon wafers is etched inside the chamber. The cleaning process includes bombarding the interior walls of the chamber with a first type of plasma in a dry cleaning operation, and then bombarding the interior walls of the chamber with a second type of plasma containing the element hydrogen in a warm-up operation. No silicon wafers need to be placed inside the chamber when the dry cleaning operation or the warm-up operation is conducted.

Abstract: A process for cleaning the interior walls of a reaction chamber after a number of silicon wafers is etched inside the chamber. The cleaning process includes bombarding the interior walls of the chamber with a first type of plasma in a dry cleaning operation, and then bombarding the interior walls of the chamber with a second type of plasma containing the element hydrogen in a warm-up operation. No silicon wafers need to be placed inside the chamber when the dry cleaning operation or the warm-up operation is conducted.

Abstract: A semiconductor wafer has a substrate, a first region in the substrate that is used for a logic circuit, and a second region in the substrate that is used for a memory cell. A first gate in the first region and a second gate in the second region are simultaneously formed on the substrate. The first gate and the second gate both include a gate dielectric layer, a polysilicon layer, a tungsten silicide layer and a cap layer, in ascending order. The cap layer and the tungsten silicide layer are then removed from the first gate. A spacer around each gate is then formed. This completes the second type MOS transistor in the memory cell of DRAM. A titanium silicide layer on the surface of the substrate adjacent to the first gate and on the surface of the polysilicon layer of the first gate is formed so as to complete the formation of the first type MOS transistor.