Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

Abstract: A power adapter can include a power input node, a communication channel node, an output node, a low-pass filter, a modulator, and a high-pass filter. The low-pass filter can include a low-pass input node coupled to the power input node and a low-pass output node coupled to the output node. The modulator can include a modulator input node coupled to the communication channel node and a modulator output node. The modulator can be configured to modulate data received from the communication channel node onto a signal having a higher frequency than a data-carrying signal carrying the data received from the communication channel node and output the modulated data to a high-pass input node of a high-pass filter. The high-pass filter can include the high-pass input node coupled to the modulator output node and a high-pass output node coupled to the output node.

Abstract: A polarization maintaining fiber array includes a substrate, a cover, and at least two polarization maintaining optical fibers. The substrate includes at least two main grooves, a first additional groove, and a second additional groove, wherein the main grooves are positioned between the first additional groove and the second additional groove. The fiber array includes at least two polarization maintaining optical fibers positioned in the at least two main grooves, a first dummy fiber positioned in the first additional groove, and a second dummy fiber positioned in the second additional groove. The cover is positioned such that it contacts the polarization maintaining optical fibers, the first dummy fiber, and the second dummy fiber.

Abstract: A polarization maintaining fiber array includes a substrate, a cover, and at least two polarization maintaining optical fibers. The substrate includes at least two main grooves, a first additional groove, and a second additional groove, wherein the main grooves are positioned between the first additional groove and the second additional groove. The fiber array includes at least two polarization maintaining optical fibers positioned in the at least two main grooves, a first dummy fiber positioned in the first additional groove, and a second dummy fiber positioned in the second additional groove. The cover is positioned such that it contacts the polarization maintaining optical fibers, the first dummy fiber, and the second dummy fiber.

Abstract: A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip.

Abstract: A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip.