Patents by Inventor Chia-Hao Chen

Chia-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973113
    Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
  • Patent number: 11973039
    Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Hao Sung, Hsuan-Yu Chen, Yu-Kai Lin
  • Patent number: 11967570
    Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: April 23, 2024
    Assignee: MediaTek Inc.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
  • Publication number: 20240128341
    Abstract: The disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a base pattern including a channel region and a drain region, a first semiconductor layer on the channel region of the base pattern, and a gate structure on the first semiconductor layer. The gate structure includes a first stack disposed on the first semiconductor layer and a second stack disposed on the first stack. The first stack includes a first sidewall adjacent to the drain region and a second sidewall opposite to the first sidewall in a first direction parallel to a top surface of the base pattern. The first sidewall is at a first distance from the second stack in the first direction, and the second sidewall is at a second distance from the second stack in the first direction. The first distance is greater than the second distance.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 18, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chia-Hao Chang, Jih-Wen Chou, Hwi-Huang Chen, Hsin-Hong Chen, Yu-Jen Huang
  • Patent number: 11962847
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 16, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 11949008
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate having a front side and a back side opposite the front side. The semiconductor structure also includes a first contact metal layer disposed on the front side of the substrate. The semiconductor structure further includes a III-V compound semiconductor layer disposed between the substrate and the first contact metal layer. Moreover, the semiconductor structure includes a via hole penetrating through the substrate and the III-V compound semiconductor layer from the back side of the substrate. The bottom of the via hole is defined by the first contact metal layer, and the first contact metal layer includes molybdenum, tungsten, iridium, palladium, platinum, cobalt, ruthenium, osmium, rhodium, rhenium, or a combination thereof.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 2, 2024
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Chia-Hao Chen
  • Patent number: 11943008
    Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: March 26, 2024
    Assignees: STMICROELECTRONICS LTD, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Chia Hao Chen, Nicolas Cordier
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 11913636
    Abstract: A light source module includes a circuit substrate, a plurality of light-emitting diodes, a cover layer and a plurality of first scattering particles. The plurality of light-emitting diodes is disposed on the circuit substrate. The cover layer covers the plurality of light-emitting diodes, and an upper surface of the cover layer has a plurality of recesses, wherein orthogonal projections of the plurality of recesses on the circuit substrate overlap the circuit substrate between the plurality of light-emitting diodes. The plurality of first scattering particles is located in the plurality of recesses.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: February 27, 2024
    Assignee: AUO Corporation
    Inventors: Hui-Chuan Chen, Chia-Hao Wu
  • Publication number: 20230383776
    Abstract: A connecting assembly is applied to connect a first housing and a second housing. The connecting assembly includes a general connecting member, a connecting base, and a clamping member. The general connecting member connects to the first housing. The general connecting member includes an accommodating portion and at least one opening. The accommodating portion is located inside the general connecting member. The opening is disposed on a side wall of the general connecting member and communicates with the accommodating portion. The connecting base is disposed on the second housing. The connecting base includes a main body disposed in the accommodating portion. The clamping member includes a flat portion and at least one clamping portion. The clamping portion extends from one end of the flat portion toward the connecting base, and the clamping portion passes through the opening and presses against the main body of the connecting base.
    Type: Application
    Filed: November 17, 2022
    Publication date: November 30, 2023
    Inventor: CHIA-HAO CHEN
  • Patent number: 11822735
    Abstract: An electronic device and a method of controlling multiple pieces of equipment are provided. The electronic device is coupled to an operating device, a first controlled device and a second controlled device. The electronic device includes an operating interface and a controlled interface. The operating interface is coupled to the operating device. The operating device includes a first operating area and a second operating area. The first operating area is configured to deliver a first operating signal. The second operating area is configured to deliver a second operating signal. The controlled interface is coupled to the first controlled device and the second controlled device. The first controlled device is controlled by the first operating signal. The second controlled device is controlled by the second operating signal.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: November 21, 2023
    Assignee: Aten International Co., Ltd.
    Inventors: Pei-Chun Lai, Kuo-Feng Kao, Chia-Hao Chen
  • Publication number: 20230170938
    Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 1, 2023
    Applicants: STMICROELECTRONICS LTD, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Chia Hao CHEN, Nicolas CORDIER
  • Publication number: 20230106612
    Abstract: A method for manufacturing an electrical package is provided. The method include: providing a substrate having a first surface and a second surface opposite to the first surface, wherein the second surface has a first level difference; forming an adhesive layer on the second surface of the substrate, wherein the adhesive layer is configured to cover the second surface and provides a third surface spaced apart from the second surface of the substrate, wherein the third surface has a second level difference; disposing a tape on the third surface of the adhesive layer; and performing a removing operation on the first surface of the substrate; wherein the second level difference is smaller than the first level difference.
    Type: Application
    Filed: October 5, 2021
    Publication date: April 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Pin HUANG, Fu Tang CHU, Pei I CHANG, Chia Hao CHEN, Tsuan Ching KUO
  • Publication number: 20230095001
    Abstract: An electronic device and a method of controlling multiple pieces of equipment are provided. The electronic device is coupled to an operating device, a first controlled device and a second controlled device. The electronic device includes an operating interface and a controlled interface. The operating interface is coupled to the operating device. The operating device includes a first operating area and a second operating area. The first operating area is configured to deliver a first operating signal. The second operating area is configured to deliver a second operating signal. The controlled interface is coupled to the first controlled device and the second controlled device. The first controlled device is controlled by the first operating signal. The second controlled device is controlled by the second operating signal.
    Type: Application
    Filed: July 8, 2022
    Publication date: March 30, 2023
    Applicant: Aten International Co., Ltd.
    Inventors: Pei-Chun Lai, Kuo-Feng Kao, Chia-Hao Chen
  • Patent number: 11588519
    Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 21, 2023
    Assignees: STMICROELECTRONICS LTD, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Chia Hao Chen, Nicolas Cordier
  • Publication number: 20220369006
    Abstract: Provided is a device comprising a frequency demodulator and an amplitude demodulator. The device is configured to use, in a first mode, both the frequency demodulator and the amplitude demodulator in parallel and to activate a radio frequency identification (RFID) card mode or a Qi charger mode based on results provided by said demodulators.
    Type: Application
    Filed: May 3, 2022
    Publication date: November 17, 2022
    Applicants: STMICROELECTRONICS LTD, STMICROELECTRONICS (ROUSSET) SAS, STMicroelectronics Razvoj Polprevodnikov D.O.O.
    Inventors: Nicolas CORDIER, Chia Hao CHEN, Karel BLAHA
  • Patent number: 11463506
    Abstract: An online file transfer tasks scheduling method for processing multiple file path access requests in a network, the method including: sending at least one file path access request to a corresponding one of at least one file access service module, executing a processing procedure in each of the at least one file access service module to generate a task package according to each received file path access request, and using one or more task execution units to process one or more of the task packages; and using a task execution unit balance module to periodically evaluate a load ratio between a plurality of the file access service modules, and determining the number of the task execution units for each file access service module according to the load ratio.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 4, 2022
    Assignee: QNAP SYSTEMS, INC.
    Inventors: Xiao-Wei Huang, Chia-Hao Chen, Chi-Lung Lin
  • Patent number: D1018441
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: March 19, 2024
    Assignee: Cheng Shin Rubber Industrial Co., Ltd.
    Inventors: Yu Chieh Chen, Yu Shiuan Lin, Chia Hao Chang, Ku Wei Liao, Yi Ru Chen