Patents by Inventor Chia-Hao SU

Chia-Hao SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996484
    Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
  • Publication number: 20240120272
    Abstract: Embodiments of the present disclosure relates to a method for forming a semiconductor device structure. The method includes including forming one or more conductive features in a first interlayer dielectric (ILD), forming an etch stop layer on the first ILD, forming a second ILD over the etch stop layer, forming one or more openings through the second ILD and the etch stop layer to expose a top surface of the one or more first conductive features, wherein the one or more openings are formed by a first etch process in a first process chamber, exposing the one or more openings to a second etch process in a second process chamber so that the shape of the or more openings is elongated, and filling the one or more openings with a conductive material.
    Type: Application
    Filed: January 15, 2023
    Publication date: April 11, 2024
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih Wei LU, Yung-Hsu WU, Cherng-Shiaw TSAI, Chia-Wei SU
  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Patent number: 11401232
    Abstract: Disclosed herein are modified chromium-dpoed zinc gallate (ZGC) nanocubes, which are characterized in respectively having a concave surface that is modified with (3-aminopropyl)triethoxysilane (APTES). The modified ZGC nanocubes produce long lasting luminescence (LLL) that lasts for at least 1.5 hours under X-ray or UV excitation. Also disclosed herein are methods for the preparation of the modified ZGC nanocubes; and methods for imaging an area of interest (e.g., cancer) in a live subject using the modified ZGC nanocubes as an imaging agent.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: August 2, 2022
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Chen-Sheng Yeh, Liu-Chun Wang, Zheng-Zhe Chen, Ping-Ching Wu, Chia-Hao Su
  • Publication number: 20210395182
    Abstract: Disclosed herein are modified chromium-dpoed zinc gallate (ZGC) nanocubes, which are characterized in respectively having a concave surface that is modified with (3-aminopropyl)triethoxysilane (APTES). The modified ZGC nanocubes produce long lasting luminescence (LLL) that lasts for at least 1.5 hours under X-ray or UV excitation. Also disclosed herein are methods for the preparation of the modified ZGC nanocubes; and methods for imaging an area of interest (e.g., cancer) in a live subject using the modified ZGC nanocubes as an imaging agent.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 23, 2021
    Inventors: Chen-Sheng YEH, Liu-Chun WANG, Zheng-Zhe CHEN, Ping-Ching WU, Chia-Hao SU