Patents by Inventor Chia-Hao SU

Chia-Hao SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237230
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Yu Lai, Jyun-Chih Lin, Yen-Ting Chen, Wei-Yang Lee, Chia-Pin Lin, Wei Hao Lu, Li-Li Su
  • Publication number: 20250062158
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base and a fin over the base. The method includes forming a first gate stack wrapped around the fin. The method includes forming a first gate spacer over a first sidewall of the first gate stack. The method includes partially removing the fin, which is not covered by the first gate stack and the first gate spacer. The method includes removing a first upper portion of the first gate stack to expose a second upper portion of the first gate spacer. The method includes removing the second upper portion of the first gate spacer. The method includes removing a first lower portion of the first gate stack and the fin originally wrapped by the first gate stack. The method includes forming a dielectric channel-cut structure in the trench.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Li CHIU, Chia-Hao Kuo, Fu-Hsiang Su, Shih-Hsun Chang
  • Publication number: 20250063789
    Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming a first interlayer dielectric structure over the source/drain epitaxial structures. The method also includes removing the first interlayer dielectric structure. The method also includes forming a recess in the source/drain epitaxial structures. The method also includes forming a silicide structure in the recess. The method also includes forming a second interlayer dielectric structure over the silicide structure.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Hsiang SU, Ping-Chun WU, Je-Wei HSU, Hong-Chih CHEN, Chia-Hao KUO, Shih-Hsun CHANG
  • Publication number: 20250048704
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of metal portions, a plurality of nanosheet structures, and a plurality of isolation structures. The metal portions are disposed on the semiconductor substrate and are spaced apart from each other. The nanosheet structures are surrounded by the metal portions such that the nanosheet structures are spaced apart from each other. The isolation structures are disposed on the semiconductor substrate such that two adjacent ones of the metal portions are isolated from each other by a corresponding one of the isolation structures. Each of the isolation structures includes a first dielectric layer and an air gap surrounded by the first dielectric layer.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 6, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hong-Chih CHEN, Fu-Hsiang SU, Shih-Hsun CHANG, Chia-Hao KUO, Chih-Ting YEH
  • Patent number: 12218227
    Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chia-Hung Chou, Chih-Hsuan Chen, Ping-En Cheng, Hsin-Wen Su, Chien-Chih Lin, Szu-Chi Yang
  • Patent number: 11401232
    Abstract: Disclosed herein are modified chromium-dpoed zinc gallate (ZGC) nanocubes, which are characterized in respectively having a concave surface that is modified with (3-aminopropyl)triethoxysilane (APTES). The modified ZGC nanocubes produce long lasting luminescence (LLL) that lasts for at least 1.5 hours under X-ray or UV excitation. Also disclosed herein are methods for the preparation of the modified ZGC nanocubes; and methods for imaging an area of interest (e.g., cancer) in a live subject using the modified ZGC nanocubes as an imaging agent.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: August 2, 2022
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Chen-Sheng Yeh, Liu-Chun Wang, Zheng-Zhe Chen, Ping-Ching Wu, Chia-Hao Su
  • Publication number: 20210395182
    Abstract: Disclosed herein are modified chromium-dpoed zinc gallate (ZGC) nanocubes, which are characterized in respectively having a concave surface that is modified with (3-aminopropyl)triethoxysilane (APTES). The modified ZGC nanocubes produce long lasting luminescence (LLL) that lasts for at least 1.5 hours under X-ray or UV excitation. Also disclosed herein are methods for the preparation of the modified ZGC nanocubes; and methods for imaging an area of interest (e.g., cancer) in a live subject using the modified ZGC nanocubes as an imaging agent.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 23, 2021
    Inventors: Chen-Sheng YEH, Liu-Chun WANG, Zheng-Zhe CHEN, Ping-Ching WU, Chia-Hao SU