Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

Abstract: The present application provides a testing apparatus. The testing apparatus includes a base; a first printed circuit board, disposed above the base; a stiffener, disposed adjacent to the base, located at a center of the base and passing through the first printed circuit board; a second printed circuit board, disposed at a center of the stiffener; and a probe card, one part thereof disposed adjacent to the stiffener and the other part thereof passing through the base, the first printed circuit board, the stiffener and the second printed circuit board. The base, the stiffener and the second printed circuit board are integrated and the base carries the first circuit board.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: The embodiments described herein relate to a reconfigurable energy storage system. In one embodiment, the reconfigurable energy storage system comprises a first energy storage system, a second energy storage system and a power converter. The power converter determines a first power level, a second power level and a load coupled to the power converter and manipulates the power transfer between the energy storage systems based on the first power level, the second power level and the load. In another embodiment, the reconfigurable energy storage system also comprises a third energy storage system. In this embodiment, the power converter determines a third power level corresponding to the third energy storage system and manipulates the power transfer between the energy storage systems based also on the third power level. The third power level may correspond to a state of charge of the third energy storage element or amount of power generated by the third energy storage system.

Abstract: A charge device coupled to an external device is provided. A connection port is configured to couple to the external device and includes a first pin and a second pin. A battery unit has a battery voltage. A conversion unit converts the battery voltage to provide power to the external device. When the battery voltage is higher than a threshold value, a detection control unit directs the first and second pins to couple to a first charge unit and the connection port outputs a first charge current to the external device. When the battery voltage is not higher than the threshold value, the detection control unit directs the first and second pins to couple to a second charge unit and the connection port outputs a second charge current to the external device. The first charge current is greater than the second charge current.

Abstract: A charge device coupled to an external device is provided. A connection port is configured to couple to the external device and includes a first pin and a second pin. A battery unit has a battery voltage. A conversion unit converts the battery voltage to provide power to the external device. When the battery voltage is higher than a threshold value, a detection control unit directs the first and second pins to couple to a first charge unit and the connection port outputs a first charge current to the external device. When the battery voltage is not higher than the threshold value, the detection control unit directs the first and second pins to couple to a second charge unit and the connection port outputs a second charge current to the external device. The first charge current is greater than the second charge current.

Abstract: An RF receiver/transmitter apparatus for carrier aggregation is disclosed, to provide a routing circuitry formed by a plurality of mixer modules for achieving both the function of carrier aggregation and the mixing frequency process of signals. This architecture allows sharing an RF front-end, improving degree of integration, and reducing hardware cost and circuitry power consumption. In addition, in the process of reception and transmission, the apparatus may perform different processing and configuration for each sub-channel to increase circuit design flexibility. The receiver apparatus includes at least one antenna, a first signal processing unit, a routing mixer device, a second signal processing unit and a digital signal processor (DSP); and the routing mixer device includes a plurality of mixer module and a plurality of current/voltage adders to achieve signal routing control through opening or closing of the mixer, switching the signal transmission path or switching the signal synthesizer.

Abstract: The embodiments described herein relate to a reconfigurable energy storage system. In one embodiment, the reconfigurable energy storage system comprises a first energy storage system, a second energy storage system and a power converter. The power converter determines a first power level, a second power level and a load coupled to the power converter and manipulates the power transfer between the energy storage systems based on the first power level, the second power level and the load. In another embodiment, the reconfigurable energy storage system also comprises a third energy storage system. In this embodiment, the power converter determines a third power level corresponding to the third energy storage system and manipulates the power transfer between the energy storage systems based also on the third power level. The third power level may correspond to a state of charge of the third energy storage element or amount of power generated by the third energy storage system.

Abstract: An RF receiver/transmitter apparatus for carrier aggregation is disclosed, to provide a routing circuitry formed by a plurality of mixer modules for achieving both the function of carrier aggregation and the mixing frequency process of signals. This architecture allows sharing an RF front-end, improving degree of integration, and reducing hardware cost and circuitry power consumption. In addition, in the process of reception and transmission, the apparatus may perform different processing and configuration for each sub-channel to increase circuit design flexibility. The receiver apparatus includes at least one antenna, a first signal processing unit, a routing mixer device, a second signal processing unit and a digital signal processor (DSP); and the routing mixer device includes a plurality of mixer module and a plurality of current/voltage adders to achieve signal routing control through opening or closing of the mixer, switching the signal transmission path or switching the signal synthesizer.