Patents by Inventor Chia-Hao Wang

Chia-Hao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250072065
    Abstract: A device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.
    Type: Application
    Filed: January 5, 2024
    Publication date: February 27, 2025
    Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Chia-Hao YU, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250063792
    Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.
    Type: Application
    Filed: December 1, 2023
    Publication date: February 20, 2025
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Chu-Yuan HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250063808
    Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: KUAN-TING PAN, JIA-CHUAN YOU, CHIA-HAO CHANG, KUO-CHENG CHIANG, CHIH-HAO WANG
  • Publication number: 20250056862
    Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20250054765
    Abstract: An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Chu-Yuan HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250056867
    Abstract: An integrated circuit includes a nanosheet transistor having a plurality of stacked channels, a gate electrode surrounding the stacked channels, a source/drain region, and a source/drain contact. The integrated circuit includes a first dielectric layer between the gate metal and the source/drain contact, a second dielectric layer on the first dielectric layer, and a cap metal on the first gate metal and on a hybrid fin structure. The second dielectric layer is on the hybrid fin structure between the cap metal and the source/drain contact.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Chia-Hao CHANG, Jia-Chuan YOU, Chu-Yuan HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12224325
    Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12219747
    Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Chih-Hsuan Chen, Kian-Long Lim, Chao-Yuan Chang, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20250040187
    Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a dielectric wall disposed over a substrate, first and second metal gate structure portions respectively disposed at either side of the dielectric wall. Each first and second metal gate structure portion includes a plurality of semiconductor layers vertically stacked and separated from each other, a high-K (HK) dielectric layer disposed to surround at least three surfaces of each of the semiconductor layers, and a gate electrode layer disposed between two neighboring semiconductor layers. The semiconductor device structure also includes a metal layer disposed on two opposing sidewalls of the dielectric wall.
    Type: Application
    Filed: December 4, 2023
    Publication date: January 30, 2025
    Inventors: Chia-Hao CHANG, Kuan-Ting PAN, Jia-Chuan YOU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250037571
    Abstract: An intrusion detection system and intrusion detection method are provided. The intrusion detection system includes multiple IoT devices and a central control device. The central control device is configured to obtain multiple sensing pairs from a paired combination of the multiple IoT devices; create a sensing-pair list including the multiple sensing pairs and features of each sensing pair; obtain multiple first pairs whose features satisfy a first feature condition from the sensing-pair list; dynamically schedule the multiple IoT devices to send and receive signals in a time sharing fashion to obtain a first sensing signal of each first pair; and based on a paired node of the multiple first pairs, count a first status code and a second status code of the multiple first pairs to which each paired node belongs, to determine whether any intrusion condition occurs.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 30, 2025
    Inventors: Chia-Lung LIU, Kuo-Hao SUNG, Hsin-Chih WANG, Ting-Wu HO, Kuei-Li HUANG
  • Patent number: 12205896
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20250022802
    Abstract: An integrated circuit (IC) with conductive structures and a method of fabricating the IC are disclosed. The method includes depositing a first dielectric layer on a semiconductor device, forming a conductive structure in the first dielectric layer, removing a portion of the first dielectric layer to expose a sidewall of the conductive structure, forming a barrier structure surrounding the sidewall of the conductive structure, depositing a conductive layer on the barrier structure, and performing a polishing process on the barrier structure and the conductive layer.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 16, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Tzu Pei Chen, Sung-Li Wang, Shin-Yi Yang, Po-Chin Chang, Yuting Cheng, Chia-Hung Chu, Chun-Hung Liao, Harry CHIEN, Chia-Hao Chang, Pinyen LIN
  • Publication number: 20240030066
    Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 25, 2024
    Inventors: Jia-Chuan You, Kuan-Ting Pan, Shi Ning Ju, Kuo-Cheng Chiang, Chia-Hao Wang
  • Publication number: 20230062311
    Abstract: A sports injury sensing system and method are provided. The sports injury sensing system includes a sports injury sensing apparatus. The apparatus receives a plurality of inertial sensing data of a user, and each of the inertial sensing data corresponds to a body part of the user. The apparatus determines an exercising body part of the user based on the inertial sensing data. The apparatus receives a thermal image sensing datum corresponding to the exercising body part, wherein the thermal image sensing datum indicates a body temperature state of the user. The apparatus analyzes a temperature change of surrounding muscles of the exercising body part based on the thermal image sensing datum. The apparatus calculates a sports injury assessment based on the inertial sensing data and the temperature change of surrounding muscles.
    Type: Application
    Filed: October 15, 2021
    Publication date: March 2, 2023
    Inventors: Zhi Ying CHEN, Hsun-Hui HUANG, Chia Hao WANG, Shr Yau JAN, Chien-Der LIN
  • Patent number: 10281809
    Abstract: The invention provides a projection apparatus and an illumination system. The projection apparatus includes an illumination system, a light valve, and a projection lens. The illumination system includes at least one laser light source, at least one light separating element, a wavelength conversion element, and a reflective element. The at least one laser light source is adapted to generate at least one laser beam, and the at least one laser beam is adapted to penetrate at least one first coating region of the light separating element. The wavelength conversion element is adapted to convert the laser beam from the light separating element into a converted beam. A second coating region of a reflective surface of the reflective element is adapted to reflect a portion of the laser beam from the wavelength conversion element, and the second coating region and the first coating region are adapted to reflect the converted beam. The portion of the laser beam and the converted beam constitute an illumination beam.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 7, 2019
    Assignee: Coretronic Corporation
    Inventors: Chia-Hao Wang, Chi-Tang Hsieh, Yao-Shun Lin
  • Publication number: 20180143519
    Abstract: The invention provides a projection apparatus and an illumination system. The projection apparatus includes an illumination system, a light valve, and a projection lens. The illumination system includes at least one laser light source, at least one light separating element, a wavelength conversion element, and a reflective element. The at least one laser light source is adapted to generate at least one laser beam, and the at least one laser beam is adapted to penetrate at least one first coating region of the light separating element. The wavelength conversion element is adapted to convert the laser beam from the light separating element into a converted beam. A second coating region of a reflective surface of the reflective element is adapted to reflect a portion of the laser beam from the wavelength conversion element, and the second coating region and the first coating region are adapted to reflect the converted beam. The portion of the laser beam and the converted beam constitute an illumination beam.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 24, 2018
    Applicant: Coretronic Corporation
    Inventors: Chia-Hao Wang, Chi-Tang Hsieh, Yao-Shun Lin
  • Patent number: 9977316
    Abstract: An illumination system includes a light integration rod and a light source module. The light integration rod has a light-in end, a light-out end opposite to the light-in end, and phosphor distributed between the light-in end and the light-out end. The light source module is configured to provide a laser beam to enter into the light integration rod through the light-in end thereof. The phosphor is used to convert the laser beam into a first color beam to form an illumination beam. The illumination beam then emits out from the light integration rod through the light-out end thereof. A projection apparatus using the aforementioned illumination system is also provided.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 22, 2018
    Assignee: CORETRONIC CORPORATION
    Inventors: Yao-Shun Lin, Chia-Hao Wang, Ko-Shun Chen
  • Patent number: 9915863
    Abstract: An illumination system including a coherent light source device, a light delivery module, and a light wavelength conversion module is provided. The coherent light source device includes a light emitting source and a light collimating element. The light emitting source is adapted to emit at least one coherent light beam. The light collimating element is located on a transmission path of the at least one coherent light beam from the light emitting source and collimates the at least one coherent light beam. The light delivery module is located on a transmission path of at least one coherent light beam from the light collimating element and includes a first lens. The first lens has a lens array surface adapted to diverge any of the coherent light beam from the light collimating element. A projection apparatus is also provided.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: March 13, 2018
    Assignee: Coretronic Corporation
    Inventors: Chia-Hao Wang, Chi-Tang Hsieh, Ko-Shun Chen, Chi-Hsun Wang
  • Publication number: 20170184950
    Abstract: A projection system including a projection apparatus and a screen is provided. The projection apparatus is adapted to output a plurality of exciting beams respectively having a plurality of different wavebands. The screen is disposed on a transmission path of the exciting beams. The screen includes a plurality of fluorescence material layers and at least one gas barrier layer. The fluorescence material layers are adapted to be excited by the exciting beams to emit image beams respectively having different wavebands, so as to form an image frame. The gas barrier layer covers the fluorescence material layers.
    Type: Application
    Filed: September 29, 2016
    Publication date: June 29, 2017
    Applicant: Coretronic Corporation
    Inventors: Yu-An Huang, Chi-Tang Hsieh, Chia-Hao Wang, Chien-Chiu Hsueh
  • Publication number: 20170153535
    Abstract: An illumination system includes a light integration rod and a light source module. The light integration rod has a light-in end, a light-out end opposite to the light-in end, and phosphor distributed between the light-in end and the light-out end. The light source module is configured to provide a laser beam to enter into the light integration rod through the light-in end thereof. The phosphor is used to convert the laser beam into a first color beam to form an illumination beam. The illumination beam then emits out from the light integration rod through the light-out end thereof. A projection apparatus using the aforementioned illumination system is also provided.
    Type: Application
    Filed: June 30, 2016
    Publication date: June 1, 2017
    Inventors: Yao-Shun Lin, Chia-Hao Wang, Ko-Shun Chen