Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

Abstract: A memory access latency estimation method includes measuring a first access latency of a first access operation of a first memory, measuring a plurality of first indexes of the first memory corresponding to the first access operation, using a plurality of first coefficients and the plurality of first indexes to perform a first weighted calculation to generate a first estimated latency, adjusting the plurality of first coefficients to generate a plurality of updated first coefficients, using the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency, and using the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.

Abstract: A method for updating software comprises transmitting a first version of the software and a first decryption key to a computing system. The method further comprises generating a second version of the software and a second decryption key. The method further comprises encrypting the second version of the software and the second decryption key. The encrypted second version of the software is configured to be decrypted using the first decryption key and not the second decryption key. The method further comprises transmitting the encrypted second version of the software and the encrypted second decryption key to the computing system.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A micro-electromechanical-system (MEMS) device may be formed to include an anti-stiction polysilicon layer on one or more moveable MEMS structures of a device wafer of the MEMS device to reduce, minimize, and/or eliminate stiction between the moveable MEMS structures and other components or structures of the MEMS device. The anti-stiction polysilicon layer may be formed such that a surface roughness of the anti-stiction polysilicon layer is greater than the surface roughness of a bonding polysilicon layer on the surfaces of the device wafer that are to be bonded to a circuitry wafer of the MEMS device. The higher surface roughness of the anti-stiction polysilicon layer may reduce the surface area of the bottom of the moveable MEMS structures, which may reduce the likelihood that the one or more moveable MEMS structures will become stuck to the other components or structures.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.

Abstract: A method of configuring a PUSCH repetition and a UE using the same method are provided. The method includes: obtaining a plurality of invalid symbol patterns; and performing a plurality of PUSCH repetition transmissions according to the plurality of invalid symbol patterns.

Abstract: A semiconductor substrate includes a plurality of transistors. A first structure is disposed over a first side of the semiconductor substrate. The first structure contains a plurality of first metallization components. A carrier substrate is disposed over the first structure. The first structure is located between the carrier substrate and the semiconductor substrate. One or more openings extend through the carrier substrate and expose one or more regions of the first structure to the first side. A second structure is disposed over a second side of the semiconductor substrate opposite the first side. The second structure contains a plurality of second metallization components.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.

Abstract: A method includes: providing a first semiconductor device including a backside interconnection structure, the first semiconductor device being formed by a semiconductor process; and generating a physical failure analysis model by an inspection process. The inspection process includes: directing an electron beam toward the frontside of the first semiconductor device; and applying an electrical signal to an electrical contact of the first semiconductor device through an electrical path that goes through a shunt board attached to a switchable interface trace bank, the electrical contact being associated with a position of the electron beam. The method further includes: generating a parameter of a revised semiconductor process according to the physical failure analysis model and the semiconductor process; and forming a second semiconductor device by the revised semiconductor process using the parameter.

Abstract: The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.

Abstract: A smart electric meter is provided. The smart electric meter includes a body, an antenna holder, an antenna structure and a supporting member. The antenna holder is disposed on the body, wherein the antenna holder is annular. The antenna structure is disposed on the antenna holder, wherein the antenna structure is moveable along a circumferential direction of the antenna holder. The supporting member is connected to the antenna structure, wherein the supporting member is moveably disposed on the antenna holder, and the supporting member moves the antenna structure along the circumferential direction of the antenna holder.

Abstract: A multiband antenna for receiving or transmitting wireless signals of a plurality of frequency bands includes a grounding sheet, formed with a hole at a first side, for providing grounding, a first micro-strip line, substantially parallel to the first side of the grounding sheet, a connecting unit, connecting to the first side of the grounding sheet and the first micro-strip line, for forming a resonant cavity with the first side of the grounding sheet and the first micro-strip line, a second micro-strip line, formed in the resonant cavity and substantially parallel to the first micro-strip line, a third micro-strip line, extending from the hole of the grounding sheet to the second micro-strip line, and a feed-in terminal, formed on the third micro-strip line within the hole, for transmitting the wireless signals.

Abstract: A smart meter capable of performing wireless transmission is used to show some power information, in which the smart meter includes an inner cylindrical case, a ring layer, an inner-layer antenna, and an outer-layer antenna. The interior of the inner cylindrical case is hollow. The ring layer surrounds the inner cylindrical case. The inner-layer antenna is attached to the ring layer and slides on the ring layer. The outer-layer antenna is also attached to the ring layer and overlaps as well as contacts with the inner-layer antenna. The inner-layer antenna and the outer-layer antenna are driven to adjust a total length of them in order to receive signals of different frequency bands.

Abstract: A three-dimensional antenna includes an L-shaped grounding element and an L-shaped radiating element. The grounding and radiating elements are arranged in a U shape. The grounding element includes a first grounding segment, a second grounding segment extending from the first grounding segment, and a short-circuit point disposed at the second grounding segment. The radiating element includes a first radiating segment opposite to the first grounding segment, a second radiating segment extending from the first radiating segment and adjacent to the second grounding segment, a feeding point disposed at the second radiating segment, and two radiator arms being able to generate respective resonant frequencies.

Abstract: An unsymmetrical dipole antenna includes a grounding element, a radiating element, and a feed-in wire. The grounding element includes a first short side metal plane and a first long side metal plane. The radiating element includes a second short side metal plane and a second long side metal plane. The feed-in wire includes a metal wire, coupled to the second short side metal plane for transmitting a feed-in signal; an insulation layer, covering the metal wire; a metal weave, covering the insulation layer, having one terminal coupled to the first short side metal plane of the grounding element, and another terminal coupled to a system ground of the wireless communication device; and a protective layer, covering the metal weave. A size of the grounding element and a size of the radiating element are irrelative.

Abstract: A smart meter capable of performing wireless transmission is used to show some power information, in which the smart meter includes an inner cylindrical case, a ring layer, an inner-layer antenna, and an outer-layer antenna. The interior of the inner cylindrical case is hollow. The ring layer surrounds the inner cylindrical case. The inner-layer antenna is attached to the ring layer and slides on the ring layer. The outer-layer antenna is also attached to the ring layer and overlaps as well as contacts with the inner-layer antenna. The inner-layer antenna and the outer-layer antenna are driven to adjust a total length of them in order to receive signals of different frequency bands.