Abstract: Embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. Once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. The leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. The circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. The comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. The circuit may include a finite state machine for managing the process.

Abstract: An apparatus, system, and method for improved memory control are provided. A circuit can include controller circuitry configured to determine, based on a speed of silicon of a memory, a read strobe code that adjusts a data clock to account for a difference between a reference clock and a data clock in terms of a number of unit intervals (UIs) and a read strobe code, a receive delay locked loop to receive the difference and delay the data clock by the number of UI and read strobe codes resulting in a delayed data clock, and a sampling amplifier to sample data from the memory based on the delayed data clock.

Abstract: An Embedded Universal Serial Bus 2.0 (USB2) device includes a physical layer having a detection mechanism to detect an Single-ended 1 (SE1) valid state and differentiate the SE1 valid state from other USB2 states.

Abstract: An Embedded Universal Serial Bus 2.0 (USB2) device includes a physical layer having a detection mechanism to detect an Single-ended 1 (SE1) valid state and differentiate the SE1 valid state from other USB2 states.

Abstract: Methods and apparatuses relating to USB high-speed chirp detection are described. In one embodiment, a bus host transceiver circuit includes a first data path to connect to a bus device, a second data path to connect to the bus device, a squelch detection circuit with a first and a second input, and a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period.

Abstract: A port is provided to facilitate a link between a first device and a second device. The port can include a driver circuit to support half duplex communication between the first device and the second device and further include switching logic to receive a value and cause the driver circuit to function in one of a plurality of half duplex modes based on the value. The value is based on a configuration register value corresponding to the port.

Abstract: Described is an apparatus which comprises: a first power supply; a second power supply lower than the first power supply; first and second transistors coupled in series and to be biased, the first and second transistors coupled to a pad; a first pull-up transistor coupled to the first power supply and to one of the first or second transistors; a pull-down transistor coupled to one of the first or second transistors; and a second pull-up transistor coupled to the second power supply, the pull-down transistor, and to one of the first or second transistors.

Abstract: Methods and apparatuses relating to USB high-speed chirp detection are described. In one embodiment, a bus host transceiver circuit includes a first data path to connect to a bus device, a second data path to connect to the bus device, a squelch detection circuit with a first and a second input, and a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period.

Abstract: An apparatus is described herein. The apparatus includes a plurality of electrical components, wherein at least one component is to increase a total impedance at a port. The apparatus also includes a comparator, wherein the comparator is to determine an additional impedance from the plurality of electrical components at the port and adjust the impedance to maintain signal integrity along a trace to the port in response to a device being coupled with the port.

Abstract: A port is provided to facilitate a link between a first device and a second device. The port can include a driver circuit to support half duplex communication between the first device and the second device and further include switching logic to receive a value and cause the driver circuit to function in one of a plurality of half duplex modes based on the value. The value is based on a configuration register value corresponding to the port.

Abstract: Embodiments include apparatuses, methods, and systems for providing a dynamic bias voltage to one or more transistors of a transceiver. In embodiments, a transceiver includes receive circuitry and transmit circuitry coupled to a same input/output (I/O) pad. A dynamic biasing circuit detects a voltage level of a data signal on the I/O pad, and generates a dynamic bias voltage having a value based on the detected voltage level. In some embodiments, the dynamic bias voltage is a selected one of a first bias voltage or a second bias voltage. The dynamic biasing circuit provides the dynamic bias voltage to one or more transistors of the transceiver to protect the transistors from electrical overstress.

Abstract: An apparatus is described herein. The apparatus includes a plurality of electrical components, wherein at least one component is to increase a total impedance at a port. The apparatus also includes a comparator, wherein the comparator is to determine an additional impedance from the plurality of electrical components at the port and adjust the impedance to maintain signal integrity along a trace to the port in response to a device being coupled with the port.

Abstract: Various embodiments include apparatus, systems, and methods having a reference node to receive a reference voltage, a first node to provide a signal, and a circuit. Such a circuit may include a second node to receive different voltages greater than the reference voltage and to cause the signal at the first node to switch between a first voltage greater than the reference voltage and a second voltage greater than the reference voltage. Other embodiments including additional apparatus, systems, and methods are described.

Abstract: Embodiments include apparatuses, methods, and systems for providing a dynamic bias voltage to one or more transistors of a transceiver. In embodiments, a transceiver may include receive circuitry and transmit circuitry coupled to a same input/output (I/O) pad. A dynamic biasing circuit may detect a voltage level of a data signal on the I/O pad, and may generate a dynamic bias voltage having a value based on the detected voltage level. In some embodiments, the dynamic bias voltage may be a selected one of a first bias voltage or a second bias voltage, The dynamic biasing circuit may provide the dynamic bias voltage to one or more transistors of the transceiver to protect the transistors from electrical overstress.

Abstract: Described is an apparatus which comprises: a first power supply; a second power supply lower than the first power supply; first and second transistors coupled in series and to be biased, the first and second transistors coupled to a pad; a first pull-up transistor coupled to the first power supply and to one of the first or second transistors; a pull-down transistor coupled to one of the first or second transistors; and a second pull-up transistor coupled to the second power supply, the pull-down transistor, and to one of the first or second transistors.

Abstract: Various embodiments include apparatus, systems, and methods having a reference node to receive a reference voltage, a first node to provide a signal, and a circuit. Such a circuit may include a second node to receive different voltages greater than the reference voltage and to cause the signal at the first node to switch between a first voltage greater than the reference voltage and a second voltage greater than the reference voltage. Other embodiments including additional apparatus, systems, and methods are described.