Patents by Inventor Chia-Hsi Chen

Chia-Hsi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240142961
    Abstract: A method of estimating greenhouse gas emission, performed by a processing device, includes: obtaining at least one time period of a number of working stations for a target manufacturing process of a product; obtaining a number of first power consumption data of the target manufacturing process, wherein the first power consumption data correspond to the working stations respectively; calculating a number of second power consumption data based on the at least one time period and the first power consumption data; searching for a number of target coefficients corresponding to the plurality of working stations respectively in coefficient database based on the target manufacturing process; and calculating greenhouse gas emission data of the target manufacturing process based on the second power consumption data and the target coefficients.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Tsung-Hsi LIN, Yun Sheng LI, Yu Ling LEE, Hsiao Pin LIN, Chia Hou CHEN
  • Publication number: 20240124844
    Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Hsin Lee, Po-Cheng Lin, Yong-Cheng Kao, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240115616
    Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20170048651
    Abstract: A state determination apparatus for a care-receiver is provided, comprising: a communication unit and a protective unit. The communication unit includes at least one first antenna module and a first wireless communication module. The protective unit is configured for accommodating the communication unit and buffering external pressure on the communication unit to protect the communication unit. The state determination apparatus is configured for being disposed on a back of a cushion. The first wireless communication module sends a detection signal through at least the first antenna module so as to communicate with a radio frequency identity (RFID) tag used by the care-receiver. After sending the detection signal, the communication unit determines whether a response signal from the RFID tag is received or information of the response signal is read so as to determine a state of the care-receiver.
    Type: Application
    Filed: August 11, 2016
    Publication date: February 16, 2017
    Applicant: Hello Nurse Medical Innovation, Inc. Taiwan Branch
    Inventors: Sharon Lin Charna, Chia Hsi Chen
  • Publication number: 20140106558
    Abstract: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.
    Type: Application
    Filed: December 31, 2013
    Publication date: April 17, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Wei Hsu, Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chih-Hsun Lin, Yen-Ming Chen, Chia-Hsi Chen, Chang-Hung Kung
  • Patent number: 8643069
    Abstract: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: February 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Wei Hsu, Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chih-Hsun Lin, Yen-Ming Chen, Chia-Hsi Chen, Chang-Hung Kung
  • Publication number: 20130015524
    Abstract: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.
    Type: Application
    Filed: July 12, 2011
    Publication date: January 17, 2013
    Inventors: Chun-Wei Hsu, Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chih-Hsun Lin, Yen-Ming Chen, Chia-Hsi Chen, Chang-Hung Kung
  • Publication number: 20120264302
    Abstract: A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Inventors: Chun-Wei Hsu, Teng-Chun Tsai, Chia-Lin Hsu, Po-Cheng Huang, Chia-Hsi Chen, Yen-Ming Chen, Chih-Hsun Lin
  • Publication number: 20120098043
    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a semiconductor device and a contact etch stop layer (CESL) and a dielectric layer covering the semiconductor device formed thereon, wherein the semiconductor device having at least a dummy gate, performing a dummy gate removal step to form at least an opening in the semiconductor device and to simultaneously remove a portion of the CESL such that a top surface of the CESL is lower than the semiconductor device and the dielectric layer and a plurality of recesses is obtained, and performing a recess elimination step to form a substantially even surface of the dielectric layer.
    Type: Application
    Filed: October 25, 2010
    Publication date: April 26, 2012
    Inventors: Ya-Hsueh Hsieh, Teng-Chun Tsai, Chia-Hsi Chen, Cheng-Huei Chang, Po-Cheng Huang, Hsin-Kuo Hsu
  • Publication number: 20080305610
    Abstract: A method of forming a shallow trench isolation structure includes steps of providing a substrate having a patterned mask layer formed thereon, wherein a trench is located in the substrate and the patterned mask layer exposes the trench. Thereafter, a dielectric layer is formed over the substrate to fill the trench. Then, a main polishing process with a first polishing rate is performed to remove a portion of the dielectric layer. An assisted polishing process is performed to remove the dielectric layer and a portion of the mask layer. The assisted polishing process includes steps of providing a slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate. Further, the mask layer is removed.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 11, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Chu Chen, Hsin-Kun Chu, Teng-Chun Tsai, Chia-Hsi Chen
  • Publication number: 20080261402
    Abstract: A method of removing an insulating layer on a substrate is described, including a first CMP process and a second CMP process performed in sequence, wherein the polishing slurry used in the first CMP process and that used in the second CMP process have substantially the same pH value that exceeds 7.0. A cleaning step is conducted between the first and the second CMP processes to remove a specific substance which would otherwise cause undesired particles to form in the second CMP process.
    Type: Application
    Filed: April 17, 2007
    Publication date: October 23, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chan Lu, Teng-Chun Tsai, Chih-Yueh Li, Kai-Gin Yang, Chien-Chung Huang, Chia-Hsi Chen, Tzu-Hui Wu
  • Publication number: 20080045014
    Abstract: A complex chemical mechanical polishing process for planarizing a structure. The process comprises steps of performing a main polishing process with a first polishing rate, wherein a slurry is provided. An assisted polishing process is then performed to planarizing the structure. The assisted polishing process comprises steps of providing the slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate.
    Type: Application
    Filed: August 18, 2006
    Publication date: February 21, 2008
    Applicant: United Microelectronics Corp.
    Inventors: Yen-Chu Chen, Hsin-Kun Chu, Teng-Chun Tsai, Chia-Hsi Chen
  • Publication number: 20070269908
    Abstract: A hybrid CMP system having a first platen and a second platen is provided. Two types of polish pads are mounted on the first platen and second platen. A lot of pattern wafers is prepared. Each pattern wafer has patterned features, and a first dielectric layer is disposed over a second dielectric layer and the patterned features. At least three foregoing pattern wafers of the lot are sequentially polished on the first platen to remove different amount of the first dielectric layer. Removal amount of each said foregoing pattern wafer is in-line measured and calculated to output a linear fitting curve of removal amount vs. polish time thereof. Based on the linear fitting curve, the rest of the pattern wafers of the same lot are sequentially polished on the first platen to reach a target thickness of remaining said first dielectric layer.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 22, 2007
    Inventors: Hsin-Kun Chu, Yen-Chu Chen, Teng-Chun Tsai, Chia-Hsi Chen