Patents by Inventor Chia Hsiang

Chia Hsiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176093
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Patent number: 11992322
    Abstract: A heart rhythm detection method and system by using radar sensor is capable of collecting an original signal using a radar sensor toward at least one subject, and converting the original signal to a two dimensional image information (i.e., spectrogram) using the concept of image vision. Then, the neural network automatically learns which heartbeat frequency should be focused on and which heartbeat frequency should be filtered out in the two dimensional image information through deep learning, so that the heartbeat frequencies can be extracted effectively.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 28, 2024
    Assignee: IONETWORKS INC.
    Inventors: Jing-Ming Guo, Ting Lin, Chia-Fen Chang, Jeffry Susanto, Yi-Hsiang Lin, Po-Cheng Huang, Yu-Wen Wei
  • Publication number: 20240170423
    Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 23, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Publication number: 20240172273
    Abstract: Examples pertaining to preamble puncturing negotiation in wireless communications are described. A station (STA) may receive a control frame, and, in response, apply the MRU pattern for one or more transmissions or receptions in a transmission opportunity (TXOP). In the control frame, either a plurality of first reserved bits in a SERVICE field or a plurality of bits in a User Info field are set to indicate a multiple resource unit (MRU) pattern regarding preamble puncturing.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Inventors: Cheng-Yi Chang, Kun-Sheng Huang, Yi-Hsuan Chung, Chung-Kai Hsu, Chia-Hsiang Chang, Kai Ying Lu
  • Patent number: 11990507
    Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 21, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 11991572
    Abstract: Methods and apparatus are provided for UE-triggered handover and early preparation with coexistence of the network-triggered handover. In one novel aspect, the UE is configured early measurement report configuration, receives an early handover command from the serving base station with a handover candidate cell list, monitors handover triggering conditions for each candidate cell on the handover candidate cell list based on a UE-triggered handover configuration and performs the UE-triggered handover to a candidate cell when the corresponding triggering condition is met for the candidate cell. In one embodiment, the UE receives a network-triggered handover command to a target cell, suspends the UE-triggered handover configuration and performs the network-triggered handover to the target cell. The UE discards the UE-triggered handover configuration upon success of the network-triggered handover and resumes the UE-triggered handover configuration upon failure of the network-triggered handover.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 21, 2024
    Assignee: MEDIATEK INC.
    Inventors: Li-Chuan Tseng, Yuanyuan Zhang, Yung-Hsiang Liu, Chun-Fan Tsai, Chia-Chun Hsu
  • Publication number: 20240156683
    Abstract: Disclosed is a reusable actuator for use with a drug container including a stopper comprising a container having a closed end, an open end, and a sidewall extending therebetween in a longitudinal direction, an electrode disposed inside the container for use in generating a gas, an actuating element disposed at and closing the open end of the container, the actuating element and the container defining an actuator interior, wherein the actuating element is movable relative to the container in the longitudinal direction by a gas pressure of the gas in the actuator interior, such that the actuating element applies a force to the stopper to cause a drug delivery from the drug container, and a retracting mechanism for use in removing the gas to assist the actuating element's retraction for reuse.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 16, 2024
    Applicant: MicroMED Co., Ltd.
    Inventors: Chia-Chi FENG, Po-Ying LI, Hong Jun YEH, Kuang-Hsiang CHENG
  • Publication number: 20240153788
    Abstract: An addition system of a reducing agent in a semiconductor manufacturing process includes pre-treatment and post-treatment gas concentration detection devices, a process exhaust gas treatment device, a reducing agent supply device, and an addition system control device. The process exhaust gas treatment device purifies exhaust gas of a semiconductor manufacturing process and emits a post-treatment gas. The reducing agent supply device supplies a reducing agent gas into the process exhaust gas treatment device. The post-treatment gas concentration detection device detects a residual concentration of the reducing agent gas in the post-treatment gas. The addition system control device calculates destruction and removal efficiency (DRE) for process gases according to pre-treatment and post-treatment gas concentrations, and, according to the DRE and the residual concentration, sends a signal to the reducing agent supply device to control the amount of the reducing agent gas added.
    Type: Application
    Filed: July 27, 2023
    Publication date: May 9, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Jia-Cheng Sun, Jui-Hsiang Cheng, I-Ling Nien, Chia-Yen Kuo, Shou-Nan Li
  • Publication number: 20240143922
    Abstract: A method of generating knowledge graph, performed by a processing device, includes: obtaining a knowledge document, performing word segmentation and part-of-speech tagging on the knowledge document to generate a number of tagged words, obtaining a number of sentences from the tagged words according to a default sentence pattern, wherein each of the sentences includes a subject, an adverb, a verb and an object, and the adverb corresponding to an adverb type, for each of the sentences, performing: using the subject as a first entity of a triple, using the object as a second entity of the triple, and using the adverb type and the verb as a relation in the triple, and forming a knowledge graph using the triple corresponding to each of the sentences.
    Type: Application
    Filed: November 14, 2022
    Publication date: May 2, 2024
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Wen-Hsiang LU, Chia-Ming TUNG, Ding-Jhe LIOU
  • Publication number: 20240145433
    Abstract: A package structure includes a first die and a second die embedded in a first molding material, a first redistribution structure over the first die and the second die, a second molding material over portions of the first die and the second die, wherein the second molding material is disposed between a first portion of the first redistribution structure and a second portion of the first redistribution structure, a first via extending through the second molding material, wherein the first via is electrically connected to the first die, a second via extending through the second molding material, wherein the second via is electrically connected to the second die and a silicon bridge electrically coupled to the first via and the second via.
    Type: Application
    Filed: January 4, 2023
    Publication date: May 2, 2024
    Inventors: Po-Yao Lin, Chia-Hsiang Lin, Chien-Sheng Chen, Kathy Wei Yan
  • Publication number: 20240137067
    Abstract: A signal transmitter may include a waveform synthesis circuit and a signal transmission circuit. The waveform synthesis circuit may store values of a reference waveform for a selected channel of the signal transmitter, and use the stored values to generate values of reference waveforms for one or more other channels of the signal transmitter. The waveform synthesis circuit may further include a sampling boost circuit to generate one or more additional values for the reference waveforms. The waveform transmission circuit may generate signals for the channels of the signal transmitter based at least in part on the values of the reference waveforms, and transmit the signals via one or more antennas.
    Type: Application
    Filed: November 1, 2023
    Publication date: April 25, 2024
    Applicant: Apple Inc.
    Inventors: Long Kong, Chia-Hsiang Chen, Utku Seckin
  • Publication number: 20240135184
    Abstract: Aspects of the disclosure provide an evolutionary neural architecture search (ENAS) method. For example, the ENAS method can include steps (a) performing one or more evolutionary operations on an initial population of neural architectures to generate offspring neural architectures, (b) evaluating performance of each of the offspring neural architectures to obtain at least one evaluation value of the offspring neural architecture with respect to a performance metric, (c) adjusting the evaluation values of the offspring neural architectures based on at least one constraint on the evaluation values, (d) selecting at least one of the offspring neural architectures as a new population of neural architectures, and (e) outputting the new population of neural architectures as a last population of neural architectures when a stopping criterion is achieved, or (f) iterating steps (a) to (d) with the new population of neural architectures being taken as the initial population of neural architectures.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yun-Chan TSAI, Min-Fong HORNG, Chia-Hsiang LIU, Cheng-Sheng CHAN, ShengJe HUNG
  • Patent number: 11964299
    Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: April 23, 2024
    Assignee: FOREMOST GOLF MFG. LTD.
    Inventors: Chia-Sheng Huang, Chi-Ling Lin, Chia-Cheng Wu, Ching-Hsiang Liu
  • Patent number: 11961770
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Publication number: 20240113639
    Abstract: A power conversion circuit for driving motor and a control method thereof are provided. The control method includes: comparing a control command with a carrier wave to acquire a PWM signal; identifying whether a phase difference between the output voltage and current falls within a range; if the phase difference falling within the range, determining whether a zero-sequence voltage is positive or negative according to the output voltage and current; injecting the zero-sequence voltage into the control command to acquire a synthesized command, and detecting maximum and minimum voltage values of the synthesized command after a period; according to the zero-sequence voltage determined to be positive or negative, selecting the maximum or minimum voltage value to perform a logic reversal operation; after stopping injecting the zero-sequence voltage, acquiring an output expected value; and comparing the output expected value with the carrier wave for adjusting a duty ratio of PWM signal.
    Type: Application
    Filed: May 9, 2023
    Publication date: April 4, 2024
    Inventors: Kuo-Heng Chao, Chia-Hsiang Chuang
  • Publication number: 20240113429
    Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.
    Type: Application
    Filed: August 16, 2023
    Publication date: April 4, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Sheng-Chin Hsu, Chia-Hung Chen, Chih-Wei Liao, Hau Yuen Tan, Hao-Hsiang Yang, Shih-Keng Huang
  • Publication number: 20240105718
    Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventors: Tao Chu, Guowei Xu, Minwoo Jang, Yanbin Luo, Feng Zhang, Ting-Hsiang Hung, Chia-Ching Lin
  • Publication number: 20240107414
    Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN
  • Publication number: 20240105770
    Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, a transistor comprises a source, a drain, and a pair of spacers between the source and the drain. In an embodiment, a semiconductor channel is between the source and the drain, where the semiconductor channel passes through the pair of spacers. In an embodiment, the semiconductor channel has a first thickness within the pair of spacers and a second thickness between the pair of spacers, where the second thickness is less than the first thickness. In an embodiment, the transistor further comprises a gate stack over the semiconductor channel between the pair of spacers.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Inventors: Tao CHU, Guowei XU, Chia-Ching LIN, Minwoo JANG, Feng ZHANG, Ting-Hsiang HUNG
  • Patent number: D1026993
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: May 14, 2024
    Assignee: HTC CORPORATION
    Inventors: Chia-Hsiang Chi, Chang-Hua Wei