Abstract: An illumination lamp system having automatic switching function for sterilization is disclosed. It contains a plurality of germicidal lighting lamp assemblies, a personnel counter, a data receiving indicator, and an ultraviolet indicator. Each germicidal lighting lamp assembly includes a lamp panel, an infrared human body sensor and a control module. The control module includes a power conversion unit, a synchronization interface, a startup circuit, a first microcontroller, and an output and input connection interface. Because the infrared human body sensor can detect the appearance of people in real time, with a synchronous voltage to switch emitting between illumination LED strips and ultraviolet germicidal light sources, in addition to effectively expanding the disinfection area, it can also safely adjust the type of light to achieve the automatic switching function for sterilization.

Abstract: A system is provided to manage on-chip memory access for multiple threads. The system comprises multiple parallel processing units to execute the threads, and an on-chip memory including multiple memory units and each memory unit includes a first region and a second region. The first region and the second region have different memory addressing schemes for parallel access by the threads. The system further comprises an address decoder coupled to the parallel processing units and the on-chip memory. The address decoder is operative to activate access by the threads to memory locations in the first region or the second region according to decoded address signals from the parallel processing units.

Abstract: Various examples with respect to compiler-allocated special registers that resolve data hazards with reduced hardware complexity are described. A processor includes a plurality of hardware components arranged in in an instruction set architecture. The processor allocates one or more forwarding registers with respect to the execution of an instruction. The processor also performs arithmetic operations based on the instruction with data input from multiple ways of the instruction set architecture such that the one or more forwarding registers is utilized for data forwarding between the multiple ways of the instruction set architecture.

Abstract: A polish head of a chemical mechanical polishing system is provided. The polish head includes a carrier head, a membrane mounted to the carrier head, an inner retaining ring mounted to the carrier head and surrounding the membrane, an outer retaining ring mounted to the carrier head and surrounding the inner retaining ring, and an image capturing device. The outer retaining ring is spaced apart from the inner retaining ring. The image capturing device is mounted to the carrier head and between the inner retaining ring and the outer retaining ring.

Abstract: A system is provided to manage on-chip memory access for multiple threads. The system comprises multiple parallel processing units to execute the threads, and an on-chip memory including multiple memory units and each memory unit includes a first region and a second region. The first region and the second region have different memory addressing schemes for parallel access by the threads. The system further comprises an address decoder coupled to the parallel processing units and the on-chip memory. The address decoder is operative to activate access by the threads to memory locations in the first region or the second region according to decoded address signals from the parallel processing units.

Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.

Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.

Abstract: The present invention provides a method to fabricate a diode whose heat stability is improved. The diode has a layer of high reflective ohmic contact and an alloy metal is used in the layer. With the alloy metal used in the layer, the heat stability of the diode is improved.

Abstract: A memory read/write arbitration method is disclosed. The memory read/write arbitration method, which is utilized in a memory controller for increasing row hit rate and decreasing the delay of memory access, comprises: providing a arbitrator; providing a read request fifo queue having command read requests; providing a write request fifo queue having command write requests; performing a judgment step for generating a priority, wherein the judgment step comprises: performing a first sub-judgment step to determine that a command read request of the command read requests has priority over a command write request of the command write requests, or the command write request can be forwarded to a second sub-judgment step under adaptive first-step conditions; performing the second sub-judgment step to determine the read request has priority over the command write request from the first sub-judgment step, or the command write request from the first sub-judgment has priority over the command read request.