Abstract: A stacked CMOS image sensor (CIS) structure is provided. The stacked CIS structure comprises a first die, a second die and a third die. The first die comprises a photodiode, a transfer gate, a selective conversion gain (SCG) switch, a reset switch, a floating node diffusion capacitor and a SCG diffusion capacitor. The second die comprises a source follower transistor and a row select switch. The third die comprises an image sensing circuit electrically connected to the third floating node.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Abstract: The compounds represented by Formula (I), which are peripheral alkyl and alkenyl chains extended benzene derivatives, are useful as dual autotaxin (ATX)/histone deacetylase (HD AC) inhibitors. These compounds may be included in a pharmaceutical composition along with a pharmaceutically acceptable carrier, and be used in a therapeutically effective amount for prophylaxis or treatment of various diseases and disorders.

Abstract: A method and wafer stack that includes a first wafer component, a second wafer component, and third wafer component. The first wafer component includes a frontside and a backside. The wafer stack also includes a second wafer component having a frontside and a backside, such that the frontside of the second wafer component is bonded to the frontside of the first wafer component. In addition, the wafer stack includes a third wafer component having a frontside and a backside, such that the frontside of the third wafer component is bonded to the backside of the second wafer component. The first wafer component includes a composite metal grid array with one or more photodiodes formed on the backside.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first fin structure and a second fin structure over a substrate, a first source/drain feature disposed over the first fin structure and a second source/drain feature disposed over the second fin structure, a dielectric feature disposed over the first source/drain feature, and a contact structure formed over the first source/drain feature and the second source/drain feature. The contact structure is electrically coupled to the second source/drain feature and is separated from the first source/drain feature by the dielectric feature.

Abstract: A method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. A contact etch stop layer (CESL) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the CESL having a snake-like pattern disposed over the substrate topography. A contact via opening is formed in a dielectric layer disposed over the CESL, where the contact via opening exposes a portion of the CESL within the trench. The portion of the CESL exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. A metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.

Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.

Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.

Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.

Abstract: A display apparatus includes a driving backplane and a light emitting component. The driving backplane has a first pad and a second pad. The light emitting component is disposed on the driving backplane. The light emitting component includes a first semiconductor layer, a second semiconductor layer, an active layer, a first electrode, a second electrode, a first solder and a second solder. The first solder and the second solder of the light-emitting component are respectively disposed on the first pad and the second pad of the driving backplane and electrically connected to the first pad and the second pad respectively. A volume of the first solder is larger than a volume of the second solder, and an area of the first pad is smaller than an area of the second pad.

Abstract: A light emitting element substrate includes a substrate and a light emitting element disposed on the substrate and including first and second semiconductor layers, an active layer, first and second electrodes, and first and second solders. The second semiconductor layer is disposed opposite to the first semiconductor layer. The active layer is disposed between the first and second semiconductor layers. The first and second electrodes are electrically connected to the first and second semiconductor layers respectively. The first and second solders are respectively disposed on and electrically connected to the first and second electrodes respectively. The first electrode includes a first under barrier pattern. The first solder covers the first under barrier pattern. A projection area of the first solder on the substrate is greater than a projection area of the first under barrier pattern on the substrate. A display apparatus is provided.

Abstract: Some embodiments relate to an IC device, including a first chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, where the second chip comprises a second plurality of conductive pad recessed and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within a first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.

Abstract: Provided are structures and methods for forming structures with surfaces having a W-shaped profile. An exemplary method includes differentially etching a gate material to a recessed surface including a first and second horn and a valley located therebetween including first and second sections and a middle section therebetween; depositing an etch-retarding layer over the recessed surface including first and second edge regions and a central region therebetween, wherein the first edge region is located over the first horn and the first section, the second edge region is located over the second horn and the second section, the central region is located over the middle region, and the central region is thicker than the first edge region and the second edge region; and performing an etch process to recess the horns to establish the gate material with a W-shaped profile.

Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. A contact etch stop layer (CESL) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the CESL having a snake-like pattern disposed over the substrate topography. A contact via opening is formed in a dielectric layer disposed over the CESL, where the contact via opening exposes a portion of the CESL within the trench. The portion of the CESL exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. A metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.

Abstract: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.

Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.

Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.