Patents by Inventor Chia-Hsing Chou

Chia-Hsing Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240428978
    Abstract: A magnetic component includes a core, a first winding, a second winding and at least one magnetic filler. The core includes an inner leg. The first winding is disposed in the core and wound around the inner leg. The second winding is disposed in the core and surrounds the first winding. At least one filling region and at least one non-filling region are formed between the first winding and the second winding. The at least one magnetic filler is filled in at least a part of the at least one filling region.
    Type: Application
    Filed: June 19, 2024
    Publication date: December 26, 2024
    Applicant: CYNTEC CO., LTD.
    Inventors: Chi-Shiuan Shie, Chia-Hsing Chou
  • Patent number: 11189654
    Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.
    Type: Grant
    Filed: June 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Publication number: 20200312894
    Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.
    Type: Application
    Filed: June 14, 2020
    Publication date: October 1, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Publication number: 20170250211
    Abstract: Semiconductor image sensor devices and manufacturing method of the same are disclosed. The semiconductor image sensor device includes a substrate, a first pixel and a second pixel, and an isolation structure. The first pixel and second pixel are disposed in the substrate, wherein the first and second pixels are neighboring pixels. The isolation structure is disposed in the substrate and between the first and second pixels, wherein the isolation structure includes a dielectric layer, and the dielectric layer includes silicon oxycarbonitride (SiOCN).
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Publication number: 20150361547
    Abstract: A method and an apparatus for forming a cleaning a chemical vapor deposition (CVD) chamber are provided. The method includes providing a chemical vapor deposition (CVD) chamber. The method further includes introducing a remote plasma source into the CVD chamber. The method also includes performing a plasma cleaning process to the CVD chamber by applying a radio-frequency (RF) power in the CVD chamber.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: Min-Hui LIN, Kuo-Hsien CHENG, Chia-Hsing CHOU, Miao-Cheng LIAO, Lai-Wan CHONG
  • Patent number: 8220144
    Abstract: A method for improving EBG (electromagnetic bandgap) structures is provided. First, a multi-layer board having at least one EBG unit is provided. Then, a maximum input impedance of the EBG unit under a predetermined frequency band is measured, in which a frequency corresponding to the maximum input impedance is a resonance frequency, and a capacitance is determined based on the resonance frequency. Besides, a minimum input impedance of the EBG unit is measured, and a logarithmic value corresponding to the maximum input impedance and a logarithmic value corresponding to the minimum input impedance are obtained so as to determine a resistance. Finally, an electronic device having the capacitance and the resistance is coupled to the EBG unit in parallel.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: July 17, 2012
    Assignee: ASUSTeK Computer Inc.
    Inventors: Chia-Hsing Chou, Chih-Wei Tsai
  • Patent number: 8059403
    Abstract: A heat dissipation device is used for dissipating heat generated from a plurality of memory modules inserted on a motherboard. The memory modules are parallel to each other. Two hooks are disposed at two ends of the slot of each memory connector, respectively, to clamp the memory module corresponding to the slot when the memory module is inserted in the slot. The heat dissipation device includes two fixing frames, a connection frame, and two fans. The two fixing frames are disposed at two opposite ends of the memory connectors and fastened with the hooks at two ends of each slot, respectively. Additionally, the connection frame is connected between the two fixing frames. The two fans are disposed on the two fixing frames, respectively. An air inlet of one of the two fans faces an air outlet of the other one.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: November 15, 2011
    Assignee: ASUSTeK Computer Inc.
    Inventors: Chia-Hsing Chou, Po-Wen Shih, Shang-Yi Wang
  • Patent number: 7957141
    Abstract: A heat-dissipating mechanism includes a first heat-dissipating device, a first positioning device, a second heat-dissipating device and a second positioning device. The first heat-dissipating device is contacted with a memory module. The first positioning device is disposed on the first heat-dissipating device and includes a protrusion. The second heat-dissipating device is connected with the first heat-dissipating device. The second positioning device has a positioning rail formed in the second heat-dissipating device and corresponding to the protrusion. The second heat-dissipating device is connected with the first heat-dissipating device when the protrusion of the first positioning device is embedded into the positioning rail second positioning device.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: June 7, 2011
    Assignee: Asustek Computer Inc.
    Inventors: Chia-Hsing Chou, Chih-Wei Tsai, Chia-Hung Lu
  • Publication number: 20100302732
    Abstract: A heat-dissipating mechanism includes a first heat-dissipating device, a first positioning device, a second heat-dissipating device and a second positioning device. The first heat-dissipating device is contacted with a memory module. The first positioning device is disposed on the first heat-dissipating device and includes a protrusion. The second heat-dissipating device is connected with the first heat-dissipating device. The second positioning device has a positioning rail formed in the second heat-dissipating device and corresponding to the protrusion. The second heat-dissipating device is connected with the first heat-dissipating device when the protrusion of the first positioning device is embedded into the positioning rail second positioning device.
    Type: Application
    Filed: August 6, 2010
    Publication date: December 2, 2010
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Chia-Hsing Chou, Chih-Wei Tsai, Chia-Hung Lu
  • Patent number: 7838777
    Abstract: A signal transmission structure including a first signal pad, a first reference plane surrounding the first signal pad, a second signal pad, a second reference plane surrounding the second signal pad, an electric conductive element, and a conductive wall is provided. The second reference plane is parallel to the first reference plane, and the electrical conductive element is connected between the first signal pad and the second signal pad to transmit a signal. The conductive wall is connected between the first reference plane and the second reference plane and surrounding the electrical conductive element. Furthermore, a package structure applying to the signal transmission structure and a bonding method thereof are provided.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: November 23, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Hsing Chou, Chih-Yi Huang
  • Patent number: 7791881
    Abstract: A heat-dissipating mechanism includes a first heat-dissipating device, a first positioning device, a second heat-dissipating device and a second positioning device. The first heat-dissipating device is contacted with a memory module. The first positioning device is disposed on the first heat-dissipating device and includes a protrusion. The second heat-dissipating device is connected with the first heat-dissipating device. The second positioning device has a positioning rail formed in the second heat-dissipating device and corresponding to the protrusion. The second heat-dissipating device is connected with the first heat-dissipating device when the protrusion of the first positioning device is embedded into the positioning rail second positioning device.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: September 7, 2010
    Assignee: Asustek Computer Inc.
    Inventors: Chia-Hsing Chou, Chih-Wei Tsai, Chia-Hung Lu
  • Publication number: 20100188817
    Abstract: A heat dissipation device is used for dissipating heat generated from a plurality of memory modules inserted on a motherboard. The memory modules are parallel to each other. Two hooks are disposed at two ends of the slot of each memory connector, respectively, to clamp the memory module corresponding to the slot when the memory module is inserted in the slot. The heat dissipation device includes two fixing frames, a connection frame, and two fans. The two fixing frames are disposed at two opposite ends of the memory connectors and fastened with the hooks at two ends of each slot, respectively. Additionally, the connection frame is connected between the two fixing frames. The two fans are disposed on the two fixing frames, respectively. An air inlet of one of the two fans faces an air outlet of the other one.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 29, 2010
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Chia-Hsing Chou, Po-Wen Shih, Shang-Yi Wang
  • Publication number: 20100060379
    Abstract: A delay line for a printed circuit board (PCB) is disclosed. The delay line includes a first straight line, a second straight line and a third straight line. The second and third straight lines are respectively disposed at two sides of the first straight line. The first, second and third straight lines are parallel to each other and form a delay path. The current direction of the second straight line is opposite to that of the third straight line.
    Type: Application
    Filed: August 30, 2009
    Publication date: March 11, 2010
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chia-Hsing Chou, Chih-Wei Tsai
  • Publication number: 20090310295
    Abstract: A heat-dissipating mechanism includes a first heat-dissipating device, a first positioning device, a second heat-dissipating device and a second positioning device. The first heat-dissipating device is contacted with a memory module. The first positioning device is disposed on the first heat-dissipating device and includes a protrusion. The second heat-dissipating device is connected with the first heat-dissipating device. The second positioning device has a positioning rail formed in the second heat-dissipating device and corresponding to the protrusion. The second heat-dissipating device is connected with the first heat-dissipating device when the protrusion of the first positioning device is embedded into the positioning rail second positioning device.
    Type: Application
    Filed: May 19, 2009
    Publication date: December 17, 2009
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Chia-Hsing Chou, Chih-Wei Tsai, Chia-Hung Lu
  • Publication number: 20090135570
    Abstract: A method for improving EBG (electromagnetic bandgap) structures is provided. First, a multi-layer board having at least one EBG unit is provided. Then, a maximum input impedance of the EBG unit under a predetermined frequency band is measured, in which a frequency corresponding to the maximum input impedance is a resonance frequency, and a capacitance is determined based on the resonance frequency. Besides, a minimum input impedance of the EBG unit is measured, and a logarithmic value corresponding to the maximum input impedance and a logarithmic value corresponding to the minimum input impedance are obtained so as to determine a resistance. Finally, an electronic device having the capacitance and the resistance is coupled to the EBG unit in parallel.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 28, 2009
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Chia-Hsing Chou, Chih-Wei Tsai
  • Publication number: 20070228578
    Abstract: A circuit substrate including a first wiring layer, a second wiring layer, a first reference plane, a second reference plane, a first conductive via, and a plurality of second conductive vias is provided. The first wiring layer and the second wiring layer have a first signal trace and a second signal trace respectively. The first conductive via is disposed between the first wiring layer and the second wiring layer for connecting the first signal trace with the second signal trace. The second conductive vias are disposed between the first reference plane and the second reference plane for connecting the first reference plane with the second reference plane, wherein the first conductive via is surrounded by the second conductive vias.
    Type: Application
    Filed: November 21, 2006
    Publication date: October 4, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: CHIA-HSING CHOU
  • Publication number: 20070221403
    Abstract: A signal transmission structure including a first signal pad, a first reference plane surrounding the first signal pad, a second signal pad, a second reference plane surrounding the second signal pad, an electric conductive element, and a conductive wall is provided. The second reference plane is parallel to the first reference plane, and the electrical conductive element is connected between the first signal pad and the second signal pad to transmit a signal. The conductive wall is connected between the first reference plane and the second reference plane and surrounding the electrical conductive element. Furthermore, a package structure applying to the signal transmission structure and a bonding method thereof are provided.
    Type: Application
    Filed: January 5, 2007
    Publication date: September 27, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Hsing Chou, Chih-Yi Huang