Patents by Inventor Chia-Hsing WU

Chia-Hsing WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378056
    Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
  • Patent number: 11784119
    Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: October 10, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming Hu, Shu-Jui Chang, Chen-Han Chou, Yen-Teng Ho, Chia-Hsing Wu, Kai-Yu Peng, Cheng-Hung Shen
  • Publication number: 20230008409
    Abstract: A device comprises a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend in a first direction above a substrate and arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are respectively on opposite sides of the gate structure.
    Type: Application
    Filed: March 23, 2022
    Publication date: January 12, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chen Han CHOU, Shu-Jui CHANG, Yen-Teng HO, Chia Hsing WU, Kai-Yu PENG, Cheng Hung SHEN, Chenming HU
  • Publication number: 20220319982
    Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.
    Type: Application
    Filed: August 23, 2021
    Publication date: October 6, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
  • Publication number: 20190315078
    Abstract: A method for making a molded composite of a prepreg sheet and a molding material includes steps of: a) providing a mold assembly, b) disposing the molding material, c) placing the prepreg sheet, d) combining a female mold and a male mold of the mold assembly, and e) operating an actuating member to press the molding material against the prepreg sheet.
    Type: Application
    Filed: September 14, 2018
    Publication date: October 17, 2019
    Inventors: Chang-Hung TSAI, Chia-Hsing WU
  • Patent number: 9534986
    Abstract: A bicycle rim examination device includes a body having a base and two upright side frames extend from the base. Each of the two side frames has a first cylinder, a second cylinder and a third cylinder connected to the top thereof. Each of the second and third cylinders is connected with a roller. A power supply device is located on one end of the body and has transmission shaft which has a roller and is driven by a motor. The transmission shaft is supported by two slides which are movable along two guide frames. A first detector with a first probe and a second detector with a second probe are connected to the body. The bicycle rim examination device examines the tension of the spokes and the roundness of the rim.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: January 3, 2017
    Assignee: ACHIMAY ENTERPRISE CO., LTD.
    Inventor: Chia-Hsing Wu
  • Publication number: 20160011081
    Abstract: A bicycle rim examination device includes a body having a base and two upright side frames extend from the base. Each of the two side frames has a first cylinder, a second cylinder and a third cylinder connected to the top thereof. Each of the second and third cylinders is connected with a roller. A power supply device is located on one end of the body and has transmission shaft which has a roller and is driven by a motor. The transmission shaft is supported by two slides which are movable along two guide frames. A first detector with a first probe and a second detector with a second probe are connected to the body. The bicycle rim examination device examines the tension of the spokes and the roundness of the rim.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 14, 2016
    Applicant: ACHIMAY ENTERPRISE CO., LTD.
    Inventor: CHIA-HSING WU
  • Patent number: 9203349
    Abstract: An ultra-wideband low-noise amplifier circuit with low power consumption includes a cascode amplifier circuit module and an output combining circuit module. The cascode amplifier circuit module receives an input signal, and outputs a first output signal and a second output signal. The output combining circuit module receives the first output signal and the second output signal, and applies respective phase shifts to the first output signal and the second output signal for reducing a phase difference between the first output signal and the second output signal, so as to obtain a combined output signal.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: December 1, 2015
    Assignee: National Chi Nan University
    Inventors: Yo-Sheng Lin, Lun-Ci Liu, Chia-Hsing Wu
  • Publication number: 20150048889
    Abstract: An ultra-wideband low-noise amplifier circuit with low power consumption includes a cascode amplifier circuit module and an output combining circuit module. The cascode amplifier circuit module receives an input signal, and outputs a first output signal and a second output signal. The output combining circuit module receives the first output signal and the second output signal, and applies respective phase shifts to the first output signal and the second output signal for reducing a phase difference between the first output signal and the second output signal, so as to obtain a combined output signal.
    Type: Application
    Filed: January 29, 2014
    Publication date: February 19, 2015
    Applicant: National Chi Nan University
    Inventors: Yo-Sheng LIN, Lun-Ci LIU, Chia-Hsing WU