Patents by Inventor Chia-Hsing WU
Chia-Hsing WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12211789Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.Type: GrantFiled: July 31, 2023Date of Patent: January 28, 2025Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming Hu, Shu-Jui Chang, Chen-Han Chou, Yen-Teng Ho, Chia-Hsing Wu, Kai-Yu Peng, Cheng-Hung Shen
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Publication number: 20240395698Abstract: A method includes following steps. A dielectric layer is formed over a substrate. A transition metal-containing layer is deposited on the dielectric layer. The transition metal-containing layer is patterned into a plurality of transition metal-containing pieces. The transition metal-containing pieces are sulfurized or selenized to form a plurality of semiconductor seeds. Semiconductor films are grown from semiconductor seeds. Transistors are formed on the semiconductor films.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
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Publication number: 20230378056Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
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Patent number: 11784119Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.Type: GrantFiled: August 23, 2021Date of Patent: October 10, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming Hu, Shu-Jui Chang, Chen-Han Chou, Yen-Teng Ho, Chia-Hsing Wu, Kai-Yu Peng, Cheng-Hung Shen
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Publication number: 20230008409Abstract: A device comprises a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend in a first direction above a substrate and arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are respectively on opposite sides of the gate structure.Type: ApplicationFiled: March 23, 2022Publication date: January 12, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chen Han CHOU, Shu-Jui CHANG, Yen-Teng HO, Chia Hsing WU, Kai-Yu PENG, Cheng Hung SHEN, Chenming HU
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Publication number: 20220319982Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.Type: ApplicationFiled: August 23, 2021Publication date: October 6, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
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Publication number: 20190315078Abstract: A method for making a molded composite of a prepreg sheet and a molding material includes steps of: a) providing a mold assembly, b) disposing the molding material, c) placing the prepreg sheet, d) combining a female mold and a male mold of the mold assembly, and e) operating an actuating member to press the molding material against the prepreg sheet.Type: ApplicationFiled: September 14, 2018Publication date: October 17, 2019Inventors: Chang-Hung TSAI, Chia-Hsing WU
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Patent number: 9534986Abstract: A bicycle rim examination device includes a body having a base and two upright side frames extend from the base. Each of the two side frames has a first cylinder, a second cylinder and a third cylinder connected to the top thereof. Each of the second and third cylinders is connected with a roller. A power supply device is located on one end of the body and has transmission shaft which has a roller and is driven by a motor. The transmission shaft is supported by two slides which are movable along two guide frames. A first detector with a first probe and a second detector with a second probe are connected to the body. The bicycle rim examination device examines the tension of the spokes and the roundness of the rim.Type: GrantFiled: July 10, 2014Date of Patent: January 3, 2017Assignee: ACHIMAY ENTERPRISE CO., LTD.Inventor: Chia-Hsing Wu
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Publication number: 20160011081Abstract: A bicycle rim examination device includes a body having a base and two upright side frames extend from the base. Each of the two side frames has a first cylinder, a second cylinder and a third cylinder connected to the top thereof. Each of the second and third cylinders is connected with a roller. A power supply device is located on one end of the body and has transmission shaft which has a roller and is driven by a motor. The transmission shaft is supported by two slides which are movable along two guide frames. A first detector with a first probe and a second detector with a second probe are connected to the body. The bicycle rim examination device examines the tension of the spokes and the roundness of the rim.Type: ApplicationFiled: July 10, 2014Publication date: January 14, 2016Applicant: ACHIMAY ENTERPRISE CO., LTD.Inventor: CHIA-HSING WU
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Patent number: 9203349Abstract: An ultra-wideband low-noise amplifier circuit with low power consumption includes a cascode amplifier circuit module and an output combining circuit module. The cascode amplifier circuit module receives an input signal, and outputs a first output signal and a second output signal. The output combining circuit module receives the first output signal and the second output signal, and applies respective phase shifts to the first output signal and the second output signal for reducing a phase difference between the first output signal and the second output signal, so as to obtain a combined output signal.Type: GrantFiled: January 29, 2014Date of Patent: December 1, 2015Assignee: National Chi Nan UniversityInventors: Yo-Sheng Lin, Lun-Ci Liu, Chia-Hsing Wu
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Publication number: 20150048889Abstract: An ultra-wideband low-noise amplifier circuit with low power consumption includes a cascode amplifier circuit module and an output combining circuit module. The cascode amplifier circuit module receives an input signal, and outputs a first output signal and a second output signal. The output combining circuit module receives the first output signal and the second output signal, and applies respective phase shifts to the first output signal and the second output signal for reducing a phase difference between the first output signal and the second output signal, so as to obtain a combined output signal.Type: ApplicationFiled: January 29, 2014Publication date: February 19, 2015Applicant: National Chi Nan UniversityInventors: Yo-Sheng LIN, Lun-Ci LIU, Chia-Hsing WU