Patents by Inventor Chia-Hsiung Hsieh
Chia-Hsiung Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9165900Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) a patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.Type: GrantFiled: February 6, 2014Date of Patent: October 20, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
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Patent number: 8786062Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.Type: GrantFiled: October 14, 2010Date of Patent: July 22, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
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Publication number: 20140151876Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Chia-Hsiung Hsieh, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh
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Patent number: 8357861Abstract: A circuit board, a chip package structure and a fabrication method of the circuit board are provided. By applying the fabrication method, a plurality of conductive channels can be formed in a single through hole of the circuit substrate. Unlike the conductive channels respectively formed in the through holes according to the related art, the conductive channels of the proposed circuit board can be formed in a single through hole. As such, it is conducive to the expansion of available layout area of the circuit board, the increase in layout flexibility, and the improvement of layout density of the circuit board.Type: GrantFiled: January 27, 2010Date of Patent: January 22, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Shih-Fu Huang, Yuan-Chang Su, Chia-Hsiung Hsieh
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Patent number: 8288869Abstract: A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.Type: GrantFiled: May 13, 2010Date of Patent: October 16, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Kuang-Hsiung Chen, Ming-Chiang Lee, Bernd Karl Appelt, Chia-Hsiung Hsieh
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Publication number: 20110084370Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.Type: ApplicationFiled: October 14, 2010Publication date: April 14, 2011Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: YUAN-CHANG SU, SHIH-FU HUANG, CHIA-CHENG CHEN, CHIA-HSIUNG HSIEH, TZU-HUI CHEN, KUANG-HSIUNG CHEN, PAO-MING HSIEH
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Publication number: 20110056736Abstract: A circuit board, a chip package structure and a fabrication method of the circuit board are provided. By applying the fabrication method, a plurality of conductive channels can be formed in a single through hole of the circuit substrate. Unlike the conductive channels respectively formed in the through holes according to the related art, the conductive channels of the proposed circuit board can be formed in a single through hole. As such, it is conducive to the expansion of available layout area of the circuit board, the increase in layout flexibility, and the improvement of layout density of the circuit board.Type: ApplicationFiled: January 27, 2010Publication date: March 10, 2011Applicant: Advanced Semiconductor Engineering, Inc.Inventors: SHIH-FU HUANG, Yuan-Chang Su, Chia-Hsiung Hsieh
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Publication number: 20100320610Abstract: A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.Type: ApplicationFiled: May 13, 2010Publication date: December 23, 2010Inventors: SHIH-FU HUANG, Yuan-Chang Su, Chia-Cheng Chen, Kuang-Hsiung Chen, Ming-Chiang Lee, Bernd Karl Appelt, Chia-Hsiung Hsieh