Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

Abstract: The present invention provides a rebar cage module comprising a first opening rebar net and a second opening rebar net. The first opening rebar net extends from a central direction, and partially forms an elongated groove shape enclosing a first accommodating portion, and has a first opening. The second opening rebar net extends from the central direction, and partially surrounds the central direction to form an elongated groove shape, and has a second opening oriented to the opposite direction with the first opening. Wherein, the first opening rebar net at least partially covers the second opening rebar net, the first opening rebar net is at least partially distributed in the second opening, and the first opening rebar net extends at least partially through the second opening into the second accommodating portion, and making the first accommodating portion and the second accommodating portion at least partially overlap.

Abstract: A stirrup module comprising an outer stirrup set, an upper-opening stirrup set having an upper opening and provided in an opening of the outer stirrup of the outer stirrup set, and a lower-opening stirrup set having a lower opening and provided in the opening of the outer stirrup of the outer stirrup set. Wherein the upper opening and the opening of the outer stirrup are oriented in the same direction, the lower opening and the upper opening are in opposite directions to each other. Wherein the upper-opening stirrup set has a first bottom of stirrup opposite to the upper opening, and the first bottom of stirrup corresponds to the position of the lower opening; the lower-opening stirrup set has a second bottom rib opposite to the lower opening, and the second bottom rib corresponds to the position of the upper opening.

Abstract: A stirrup module includes first, second, third and third erect bar portions, a bottom rib section. The second erect bar portion is arranged in parallel with the first erect bar portion. The third erect bar portion is arranged in parallel with the first erect bar portion and located between the first and second erect bar portions. The fourth erect bar portion is arranged in parallel with the first erect bar portion and located between the third and the second erect bar portions. A first gap is between the first and third erect bar portions, and a second gap is between the second and fourth erect bar portions. The bottom rib section connects at least portion of the bottom ends of the first, second, third and fourth erect bar portions, and the first and second gaps are each formed with an opening at the end opposite to the bottom rib section.

Abstract: A boost converter includes an inductor and a diode electrically connected in series between an input voltage and an output voltage; a transistor electrically coupled to an interconnected node of the inductor and the diode; and a controller that controls switching of the transistor according to a transient mode and an estimated load current. The output voltage in a light-to-heavy load transient mode has at least one first valley point with a value of a transient voltage threshold, followed by at least one second valley point with a value higher than the first valley point, before exiting the light-to-heavy load transient mode.

Abstract: A boost converter includes an inductor and a diode electrically connected in series between an input voltage and an output voltage; a transistor electrically coupled to an interconnected node of the inductor and the diode; and a controller that controls switching of the transistor according to a transient mode and an estimated load current. The output voltage in a light-to-heavy load transient mode has at least one first valley point with a value of a transient voltage threshold, followed by at least one second valley point with a value higher than the first valley point, before exiting the light-to-heavy load transient mode.

Abstract: A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor.

Abstract: A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor.