Patents by Inventor Chia Hsuan Lee

Chia Hsuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957587
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin
  • Publication number: 20210083868
    Abstract: A dynamic secret key security system for test circuit and a method of the same are disclosed. The security architecture includes a scan chain set, a dynamic key generator, a secret key checking logic, a fake response generator, and a controller. Scan chains of the scan chain set receive a test vector while the dynamic key generator produces different secret keys according to the test vector received. The secret key checking logic is used for comparing the test vector with the secret key so as to know whether they are the same. Thus whether the test vector being input is legal can be learned. Thereby the present dynamic secret key generation technique provides higher security level. Moreover, the secret key will not be stored in the memory in advance so that attackers cannot get the secret key through attacks on the memory.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: KUEN-JONG LEE, CHIA-CHI WU, MAN-HSUAN KUO
  • Publication number: 20210082768
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 18, 2021
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 10937691
    Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
  • Patent number: 10930502
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of isolation structures on the semiconductor substrate, and a plurality of blocking structures disposed directly over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hsuan Yang, Wen Han Hung, Tzy-Kuang Lee, Chia Ying Lin
  • Publication number: 20210047094
    Abstract: The invention discloses a reticle storage device including a top lid, a bottom lid and a soft contact member. The top lid has a ceiling and a cover surrounding the ceiling. The bottom lid has a carrier and a peripheral structure surrounding the carrier. The soft contact member is configured to laterally extend in between the cover and the peripheral structure when the top lid and the bottom lid engage with each other, and to extend from an inside to an outside of the device in order to buffer the contact among the two lids.
    Type: Application
    Filed: July 15, 2020
    Publication date: February 18, 2021
    Inventors: CHIA-HO CHUANG, Hsin-Min HSUEH, Yi-Hsuan Lee, Hsing-Min Wen, Ming-Chien CHIU
  • Publication number: 20210048755
    Abstract: A reticle storage device includes a top lid having a ceiling and a cover surrounding the ceiling, and a bottom lid having a carrier and a peripheral structure surrounding the carrier. When the top lid engages with the bottom lid, a passage is defined therebetween and therefore the reticle storage device is not sealed.
    Type: Application
    Filed: July 8, 2020
    Publication date: February 18, 2021
    Inventors: Chia-Ho Chuang, Hsing-Min Wen, Hsin-Min Hsueh, Yi-Hsuan Lee, Ming-Chien Chiu
  • Publication number: 20200397940
    Abstract: An air purifier and a purifying method are provided. The air purifier includes a housing, a sterilization and ozone-generating unit, a physical filter, a first ozone-removing unit, and a cover. The housing has a sidewall and a bottom surface to define a processing space, wherein an upper end of the housing has an air inlet and the sidewall has an air outlet. The sterilization and ozone-generating unit is disposed in the processing space. The physical filter is disposed in the processing space, extends along the sidewall, and surrounds the sterilization and ozone-generating unit. The first ozone-removing unit is disposed between the physical filter and the sidewall. The cover is openably disposed at the air inlet.
    Type: Application
    Filed: September 4, 2019
    Publication date: December 24, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: I-Ling Nien, Shou-Nan Li, Meng-Hsuan Lee, Hui-Ya Shih, Wen-An Xie, Yen-An Chen, Chia-Yen Kuo
  • Publication number: 20200366782
    Abstract: The present invention provides a wireless communication device and a subscriber identity module card in a wireless communication device. The subscriber identity module card comprises a flat plate carrier, a subscriber identity module circuit and a gas sensing chip. The flat plate carrier comprises a first surface where the subscriber identity module circuit is disposed, a second surface where the gas sensing chip is disposed, a through hole, and an electrical contact portion passing through the through hole and extending to reach the first surface and the second surface. The electrical contact portion is electrically connected to the subscriber identity module circuit and the gas sensing chip. The gas sensing chip is disposed on a portion of the subscriber identity module card where not occupied by the subscriber identity module circuit. Thus, the wireless communication device provides gas sensing function without additionally equipping with an external gas sensing element.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 19, 2020
    Inventors: Yu-Hsuan Liao, Chia-Pin Huang, Chun-Hsien Tsai, Ting-Chuan Lee, Chun-Jung Tsai
  • Patent number: 10777504
    Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ta Yu, Kai-Hsuan Lee, Yen-Ming Chen, Chi On Chui, Sai-Hooi Yeong
  • Publication number: 20200283288
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming Yen LEE, Chia-Hao SUNG, Ching-Han HUANG, Yu-Hsuan TSAI
  • Patent number: 10770555
    Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure disposed on a semiconductor substrate, a sidewall spacer disposed on sidewalls of the gate structure, a lightly-doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure, a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer, a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly-doped source/drain region, and a counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly-doped source/drain region and the halo implant region. The dopant concentration of the counter-doping region is lower than the dopant concentration of the halo implant region.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: September 8, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Hsuan Wang, Kan-Sen Chen, Sing-Lin Wu, Yung-Lung Chou, Yun-Chou Wei, Chia-Hao Lee, Chih-Cherng Liao
  • Patent number: 10689248
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 23, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming Yen Lee, Chia Hao Sung, Ching-Han Huang, Yu-Hsuan Tsai
  • Publication number: 20200193676
    Abstract: Methods and apparatus of processing 360-degree virtual reality images are disclosed. According to one method, the method receives coded data for an extended 2D (two-dimensional) frame including an encoded 2D frame with one or more encoded guard bands, wherein the encoded 2D frame is projected from a 3D (three-dimensional) sphere using a target projection, wherein said one or more encoded guard bands are based on a blending of one or more guard bands with an overlapped region when the overlapped region exists. The method then decodes the coded data into a decoded extended 2D frame including a decoded 2D frame with one or more decoded guard bands, and derives a reconstructed 2D frame from the decoded extended 2D frame.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 18, 2020
    Inventors: Cheng-Hsuan SHIH, Chia-Ying LI, Ya-Hsuan LEE, Hung-Chih LIN, Jian-Liang LIN, Shen-Kai CHANG
  • Publication number: 20200161240
    Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.
    Type: Application
    Filed: December 20, 2019
    Publication date: May 21, 2020
    Inventors: Chia-Ta YU, Kai-Hsuan LEE, Yen-Ming CHEN, Chi On CHUI, Sai-Hooi YEONG
  • Patent number: 10658296
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Publication number: 20200152522
    Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Bo-Yu Lai, Bo-Cyuan Lu, Chi On Chui, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200152648
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Patent number: 10643892
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: D890336
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 14, 2020
    Assignee: MEDIMAGING INTEGRATED SOLUTION, INC.
    Inventors: Chung-Hsuan Lee, Yi-Han Huang, Chia-Jung Lee, Yu-Tsung Lee