Abstract: A method performed by a User Equipment (UE) for Layer 1/Layer 2 Triggered Mobility (LTM) is provided. The method receives, from a source cell, a Cell Switch Command (CSC) Medium Access Control (MAC) Control Element (CE), the CSC MAC CE indicating a target cell, Timing Advance (TA) information, and a Transmission Configuration Indicator (TCI) state. The method determines whether the TA information is valid. In a case that the TA information is valid, the method determines a pathloss based on a pathloss reference signal associated with the TCI state. In a case that the TA information is not valid, the method determines whether the CSC MAC CE includes Contention-Free Random Access (CFRA) information, and then determines the pathloss based on a Synchronized Signal Block (SSB) indicated in the CFRA information in a case that the CSC MAC CE includes the CFRA information.

Abstract: A method for configuring a subsequent conditional primary secondary cell addition/change (S-CPAC) to a UE is provided. The method receives from a source cell an S-CPAC configuration that includes an RRC configuration for a primary secondary cell (PSCell) and a set of conditions for switching to the PSCell. The method receives a secondary key (SK)-counter list associated with the S-CPAC. The list includes one or more SK-counter entries arranged in an order. The method stores the S-CPAC configuration and the SK-counter list. After determining that one or more of the set of conditions are satisfied, the method selects a first SK-counter entry of the SK-counter list and configures the UE with the S-CPAC configuration to switch from another PSCell to the PSCell. In configuring the UE with the S-CPAC configuration, the first SK-counter entry is applied. The method then removes the first SK-counter entry from the SK-counter list.

Abstract: A machine learning training device is disclosed. The machine learning training device includes a virtual hard anchor generation circuit, a classification circuit and a training circuit. The virtual hard anchor generation circuit is configured to generate several virtual hard anchors according to several easy samples classified into several types. The virtual hard anchors respectively correspond to one of the several types. The classification circuit is configured to classify several hard samples into several types according to virtual hard anchors. Parts of the hard samples classified into several types are several clean hard samples. Another parts of the hard samples that are not classified into several types are several noisy hard samples. The training circuit is configured to perform machine learning training according to several easy samples and several clean hard samples.

Abstract: A Static Radom Access Memory (SRAM) cell includes a pass-gate transistor and a pull-down transistor. The pass-gate transistor includes a first active region and a first gate structure engaging the first active region. The pull-down transistor includes a second active region and a second gate structure engaging the second active region. The SRAM cell further includes a first isolation feature abutting the first gate structure and a second isolation feature abutting the second gate structure. The first isolation feature is spaced from the first active region of the pass-gate transistor for a first distance. The second isolation feature is spaced from the second active region of the pull-down transistor for a second distance that is larger than the first distance.

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

Abstract: The present invention provides a method for preparing an activated carbon, which includes impregnating a carbonaceous material with carbonated water; and exposing the carbonaceous material to microwave radiation to produce the activated carbon.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: The present disclosure provides a package device and a manufacturing method thereof. The package device includes an electronic device, a conductive pad having a first bottom surface, and a redistribution layer disposed between the conductive pad and the electronic device. The redistribution layer has a second bottom surface, and the conductive pad is electrically connected to the electronic device through the redistribution layer. The first bottom surface is closer to the electronic device than the second bottom in a normal direction of the electronic device.

Abstract: A wafer map recognition method using artificial intelligence includes obtaining wafer maps of a plurality of wafers; performing an unsupervised algorithm on the wafer map of each wafer in the plurality of wafers to generate a feature data set for the corresponding wafer map; and performing a clustering algorithm according to a plurality of feature data sets for the plurality of wafer maps to find a wafer map with a potential defect.

Abstract: A method for performing an RA procedure for LTM is provided. The method receives a PDCCH order for initiating the RA procedure for an LTM candidate cell. The PDCCH order indicates that an index of a preamble is not “0.” The PDCCH order includes a first DCI field indicating that a transmission of the preamble is an initial transmission or a re-transmission and a second DCI field indicating the LTM candidate cell. The method increments a power ramping counter by 1 when the first DCI field indicates the re-transmission and the PDCCH order indicates an SSB for the re-transmission of the preamble. The SSB is the same as an SSB used in a previous transmission of the preamble. The method sets, based on the incremented power ramping counter, a power parameter. The method re-transmits, to the LTM candidate cell, the preamble based on at least the set power parameter.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.

Abstract: A thermoset epoxy resin, its preparing composition and making process are disclosed. In particular, the thermoset epoxy resin is glycidyl ether of diphenolic bis-carbamate and formed by curing a one component epoxy composition and has a general structure as shown in formula (1).

Abstract: A thermoset epoxy resin, its preparing composition and making process are disclosed. In particular, the thermoset epoxy resin is glycidyl ether of diphenolic bis-carbamate and formed by curing a one component epoxy composition and has a general structure as shown in formula (1).

Abstract: The present disclosure provides a method for disease control of plants, comprising predicting the probability of a disease occurrence and suggesting a suitable and effective control measure for the identified pathogen and/or host. The present disclosure also provides an advisory service with recommended management actions and other alerts and notifications.

Abstract: A frequency-changing control apparatus includes a rectification circuit, a control circuit, and a frequency-changing driving circuit. The control circuit includes a microprocessor. The frequency-changing control apparatus has variable voltage variable frequency for driving a motor. A temperature detection unit and an alarm device are connected to the microprocessor. The temperature detection unit is able to detect the temperature of the circumstance and convert a temperature value into a signal to be transmitted to the microprocessor for generating an alarm effect via the alarm device so that the operator could know the time of maintenance beforehand, preventing the apparatus from stopping suddenly because of superheat. The present invention is able to decrease the reject rate, reduce the loss of material, and cut down the maintenance cost.

Abstract: A liquid crystal display panel is provided. The liquid crystal display panel includes a plurality of pixel units, a first common voltage region and a second common voltage region. The pixel units include a first group of pixel units and a second group of pixel units arranged in rows and columns. The first common voltage region carries a first alternating current thereon and is electrically connected to the first group of pixel units. The second common voltage region carries a second alternating current thereon and is electrically connected to the second group of pixel units.