Patents by Inventor Chia-Hua Chou

Chia-Hua Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10539972
    Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 21, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chin-Hsun Chen, Hao-Yuan Lin, Chia-Hua Chou
  • Patent number: 10444779
    Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: October 15, 2019
    Assignee: MEDIATEK INC.
    Inventors: Hao-Yuan Lin, Chia-Hua Chou, Yen-Hsun Hsu
  • Patent number: 10326361
    Abstract: A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result. The low dropout regulator also includes a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result. The low dropout regulator also includes an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 18, 2019
    Assignee: MediaTek Inc.
    Inventors: Nien-Hui Kung, Chia-Hua Chou, Yen-Hsun Hsu
  • Publication number: 20180262105
    Abstract: A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result. The low dropout regulator also includes a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result. The low dropout regulator also includes an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.
    Type: Application
    Filed: February 27, 2018
    Publication date: September 13, 2018
    Applicant: MediaTek Inc.
    Inventors: Nien-Hui Kung, Chia-Hua Chou, Yen-Hsun Hsu
  • Publication number: 20180120880
    Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.
    Type: Application
    Filed: October 12, 2017
    Publication date: May 3, 2018
    Inventors: Hao-Yuan Lin, Chia-Hua Chou, Yen-Hsun Hsu
  • Publication number: 20180120874
    Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 3, 2018
    Inventors: Chin-Hsun Chen, Hao-Yuan Lin, Chia-Hua Chou
  • Patent number: 9886044
    Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: February 6, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chin-Hsun Chen, Hao-Yuan Lin, Chia-Hua Chou
  • Publication number: 20170308153
    Abstract: A power delivery system for a multi-core processor chip includes: a plurality of first power delivery units and a plurality of second power delivery units. The plurality of first power delivery units are coupled to a first power supply device. Each of the first power delivery units is arranged to supply power from the first power supply device to a core of the multi-core processor chip. The plurality of second power delivery units are coupled to a second power supply device. Each of the second power delivery units is arranged to selectively supply power from the second power supply to a core of the multi-core processor chip according to a level of a core voltage required by the core of the multi-core processor chip.
    Type: Application
    Filed: February 20, 2017
    Publication date: October 26, 2017
    Inventors: Chia-Hua Chou, Yen-Hsun Hsu
  • Publication number: 20170038783
    Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.
    Type: Application
    Filed: February 15, 2016
    Publication date: February 9, 2017
    Inventors: Chin-Hsun CHEN, Hao-Yuan LIN, Chia-Hua CHOU
  • Patent number: 8451150
    Abstract: A transceiver includes an analog-to-digital converter (ADC) having an embedded processing circuit and an embedded digital-to-analog converting (DAC) unit. The ADC is arranged to convert an analog input signal into a digital output signal during a first operational phase of the transceiver. The embedded processing circuit is arranged to generate a digital code according to the analog input signal and an analog signal. The DAC unit is coupled to the embedded processing circuit, wherein the embedded DAC unit is arranged to convert the digital code into the analog signal during the first operational phase, and is arranged to convert a digital input signal into an analog output signal during a second operational phase of the transceiver.
    Type: Grant
    Filed: April 11, 2010
    Date of Patent: May 28, 2013
    Assignee: Mediatek Inc.
    Inventor: Chia-Hua Chou
  • Patent number: 8111178
    Abstract: A capacitor array includes a plurality of capacitor components each having a first node and a second node, and first nodes of the capacitor components are coupled to each other. A calibration method for the capacitor array utilizes a calibration capacitor component to couple the first nodes. Then, the calibration method determines a capacitance indication value regarding the specific capacitor component by coupling different references voltage to a second node of the specific capacitor component and coupling different test voltages to a second node of the calibration capacitor component. Accordingly, the calibration method calibrates the capacitance mismatches of the capacitor array in the digital domain.
    Type: Grant
    Filed: November 26, 2009
    Date of Patent: February 7, 2012
    Assignee: Mediatek Inc.
    Inventors: Chieh-Wei Liao, Chia-Hua Chou, Tse-Hsiang Hsu, Wen-Hua Chang
  • Publication number: 20110249710
    Abstract: A transceiver includes an analog-to-digital converter (ADC) having an embedded processing circuit and an embedded digital-to-analog converting (DAC) unit. The ADC is arranged to convert an analog input signal into a digital output signal during a first operational phase of the transceiver. The embedded processing circuit is arranged to generate a digital code according to the analog input signal and an analog signal. The DAC unit is coupled to the embedded processing circuit, wherein the embedded DAC unit is arranged to convert the digital code into the analog signal during the first operational phase, and is arranged to convert a digital input signal into an analog output signal during a second operational phase of the transceiver.
    Type: Application
    Filed: April 11, 2010
    Publication date: October 13, 2011
    Inventor: Chia-Hua Chou
  • Publication number: 20110122006
    Abstract: A capacitor array includes a plurality of capacitor components each having a first node and a second node, and first nodes of the capacitor components are coupled to each other. A calibration method for the capacitor array utilizes a calibration capacitor component to couple the first nodes. Then, the calibration method determines a capacitance indication value regarding the specific capacitor component by coupling different references voltage to a second node of the specific capacitor component and coupling different test voltages to a second node of the calibration capacitor component. Accordingly, the calibration method calibrates the capacitance mismatches of the capacitor array in the digital domain.
    Type: Application
    Filed: November 26, 2009
    Publication date: May 26, 2011
    Inventors: Chieh-Wei Liao, Chia-Hua Chou, Tse-Hsiang Hsu, Wen-Hua Chang
  • Patent number: 7729214
    Abstract: An apparatus for obtaining a push-pull signal is disclosed. The apparatus includes: a first amplifier coupled to a first fluctuating signal for utilizing a first gain value to amplify the first fluctuating signal and then outputting a first amplified fluctuating signal; a second amplifier coupled to a second fluctuating signal for utilizing a second gain value to amplify the second fluctuating signal and then outputting a second amplified fluctuating signal; a subtractor electrically connected to the first and second amplifiers for subtracting the second amplified fluctuating signal from the first amplified fluctuating signal to generate the push-pull signal; and a level decision unit electrically connected to the first and second amplifiers for controlling the amplitudes of signals amplified by the first and second amplifiers when the optical disc drive is switched from a first operating mode to a second operating mode.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: June 1, 2010
    Assignee: MediaTek Inc.
    Inventors: Chia-Hua Chou, Chin-Yuan Hu, Ming-Jiou Yu
  • Patent number: 7706239
    Abstract: An apparatus for detecting a pre-pit signal at different laser power intensities of an optical disk drive. The apparatus includes an amplifier for receiving a push-pull signal acquired from an optical disk to generate an adjusted signal, a multiplexer for receiving the push-pull signal and the adjusted signal and selecting the push-pull signal or the adjusted signal as a slicing signal for output according to a power state signal, and a slicer for receiving the slicing signal and slicing the slicing signal according to a slicing level to generate the pre-pit signal. Thus, the apparatus only needs one set of slicer to correctly slice the pre-pit signal.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: April 27, 2010
    Assignee: Mediatek Inc.
    Inventors: Tse-Hsiang Hsu, Chia-Hua Chou
  • Patent number: 7693011
    Abstract: The invention provides a wobble detection circuit. An exemplary embodiment of the wobble detection circuit comprises an automatic gain control module, an analog to digital converter, a digital band pass filter, and a digital band pass filter. The automatic gain control module amplifies a first input signal and a second input signal detected by a pickup head to the same magnitude to obtain a first amplified signal and a second amplified signal. The adder then subtracts the second amplified signal from the first amplified signal to obtain an analog wobble signal. The analog to digital converter then converts the analog wobble signal to a first digital wobble signal. Finally, the digital band pass filter accepts frequency components of the first digital wobble signal within a pass band and rejects frequency components of the first digital wobble signal outside the pass band to obtain a second digital wobble signal.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: April 6, 2010
    Assignee: Mediatek Inc.
    Inventors: Yuh Cheng, Chih-Ching Chen, Chia-Wei Liao, Ming-Jiou Yu, Kuo-Jung Lan, Shu-Hung Chou, Bing-Yu Hsieh, Chia-Hua Chou
  • Patent number: 7586822
    Abstract: An optical disk drive includes an optical disk drive controller that can test the write channels between the controller and the laser diode driver. Using the results of this testing, the optical disk drive controller adjusts the characteristics of the write channel signals provided to the laser diode driver to correct for one or more detected imperfections in the write channel signals. Both the optical disk drive controller and the laser diode driver have communications ports to facilitate communication. The optical disk drive controller programs the operating characteristics of the laser diode driver so that the laser diode driver can be optimized for the measured characteristics of the write channels.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: September 8, 2009
    Assignee: MediaTek Inc.
    Inventors: Chia-Hua Chou, Chih-Cheng Chen
  • Patent number: 7545221
    Abstract: The present invention provides a signal amplifying apparatus, for converting a first input signal into a first output signal. The signal amplifying apparatus includes an input stage circuit for receiving the first input signal; a cascoded circuit coupled to the input stage circuit, including a plurality of first cascoded transistors, wherein equivalent oxide thicknesses of the first cascoded transistors are not the same; an output stage circuit has a first input port coupled to the cascoded circuit, and a first output port for outputting the first output signal; and a first capacitor has a first terminal connected to the first output port of the output stage circuit and a second terminal coupled to the cascoded circuit, wherein the second terminal is not connected to the first input port of the output stage circuit.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: June 9, 2009
    Assignee: Mediatek Inc.
    Inventors: Chia-Hua Chou, Kang-Wei Hsueh
  • Patent number: 7479811
    Abstract: A sample/hold circuit module. The sample/hold circuit module comprises a sample/hold circuit, an S/H controller, a pass transistor, and a high voltage generator. The sample/hold circuit comprises a capacitor and a sampling switch. The capacitor has a first electrode coupled to a first fixed voltage and a second electrode coupled to an output node of the sample/hold circuit module. The sampling switch comprises an output terminal coupled to the second electrode of the capacitor, an input terminal, and a control terminal. The S/H controller is coupled between the control terminal of the sampling switch and a second fixed voltage. The pass transistor has a sampling input terminal, an output terminal coupled to the input terminal of the sampling switch, and a control terminal. The high voltage generator is coupled between the control terminal of the pass transistor and the second fixed voltage.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: January 20, 2009
    Assignee: Mediatek Inc.
    Inventors: Chia-Hua Chou, Tse-Hsiang Hsu
  • Patent number: 7477589
    Abstract: The present invention with an optical disk drive controller and an optical pickup head connected together by a flexible cable is described. The device includes a delay adjusting module located within the first module for delaying a first signal by an amount specified by a calibration signal. The first module transmits the delayed first signal and a second signal through a first signal channel and a second signal channel, respectively, to the second module of the optical pickup head, a monitoring module located within the optical pickup head for receiving and reshaping the delayed first signal and the second signal so as to generate a monitor signal. A calibration signal-generating module is located within the optical disk drive controller for receiving the monitor signal so as to generate the calibration signal.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: January 13, 2009
    Assignee: Mediatek Incorporation
    Inventors: Chia-Hua Chou, Chih-Cheng Chen