Patents by Inventor Chia-Hua Chou
Chia-Hua Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11867732Abstract: An output voltage protection controller includes a comparator circuit and a voltage adjustment circuit. The comparator circuit compares a first voltage signal with a second voltage signal to generate a control signal that controls output voltage protection of a voltage regulator, wherein one of the first voltage signal and the second voltage signal is a feedback voltage derived from an output voltage of the voltage regulator, and another of the first voltage signal and the second voltage signal is a voltage detection threshold. The voltage adjustment circuit injects an offset voltage to the second voltage signal for dynamically adjusting the second voltage signal during a period in which a target regulated voltage level of the output voltage is a constant.Type: GrantFiled: February 13, 2022Date of Patent: January 9, 2024Assignee: MediaTek Singapore Pte. Ltd.Inventors: Nien-Hui Kung, Chia-Hua Chou
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Patent number: 11848606Abstract: The present invention provides a device including a first power delivery channel and a second power delivery channel. The first power delivery channel includes a first voltage regulator, wherein the first voltage regulator is configured to receive a first input voltage to generate a first output signal. The second power delivery channel includes a second voltage regulator and a third voltage regulator, wherein the second voltage regulator receives a second input voltage to generate a second output signal, and the third voltage regulator receives the second output signal to generate a converted second output signal, wherein the first output signal and the converted second output signal are coupled together to a core circuit.Type: GrantFiled: April 21, 2022Date of Patent: December 19, 2023Assignee: MEDIATEK INC.Inventors: Chia-Hua Chou, Yen-Hsun Hsu
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Publication number: 20230231482Abstract: A voltage regulator with dynamic voltage and frequency tracking is shown. The voltage regulator has power switches converting an input voltage into an output voltage, a control loop, a voltage comparator, and a target voltage generator. The control loop is coupled to the power switches to control the power switches to perform voltage regulation. The voltage comparator compares the output voltage to the target voltage to generate a first control signal to control the control loop. The target voltage generator generates the target voltage for the voltage comparator based on the frequency difference between the target frequency and the critical-path-related frequency, wherein the critical-path-related frequency depends on the output voltage. The power efficiency and response time are improved.Type: ApplicationFiled: November 21, 2022Publication date: July 20, 2023Inventors: Nien-Hui KUNG, Chia-Hua CHOU
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Publication number: 20220376615Abstract: The present invention provides a device including a first power delivery channel and a second power delivery channel. The first power delivery channel includes a first voltage regulator, wherein the first voltage regulator is configured to receive a first input voltage to generate a first output signal. The second power delivery channel includes a second voltage regulator and a third voltage regulator, wherein the second voltage regulator receives a second input voltage to generate a second output signal, and the third voltage regulator receives the second output signal to generate a converted second output signal, wherein the first output signal and the converted second output signal are coupled together to a core circuit.Type: ApplicationFiled: April 21, 2022Publication date: November 24, 2022Applicant: MEDIATEK INC.Inventors: Chia-Hua Chou, Yen-Hsun Hsu
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Publication number: 20220357373Abstract: An output voltage protection controller includes a comparator circuit and a voltage adjustment circuit. The comparator circuit compares a first voltage signal with a second voltage signal to generate a control signal that controls output voltage protection of a voltage regulator, wherein one of the first voltage signal and the second voltage signal is a feedback voltage derived from an output voltage of the voltage regulator, and another of the first voltage signal and the second voltage signal is a voltage detection threshold. The voltage adjustment circuit injects an offset voltage to the second voltage signal for dynamically adjusting the second voltage signal during a period in which a target regulated voltage level of the output voltage is a constant.Type: ApplicationFiled: February 13, 2022Publication date: November 10, 2022Applicant: MediaTek Singapore Pte. Ltd.Inventors: Nien-Hui Kung, Chia-Hua Chou
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Patent number: 10539972Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.Type: GrantFiled: December 26, 2017Date of Patent: January 21, 2020Assignee: MEDIATEK INC.Inventors: Chin-Hsun Chen, Hao-Yuan Lin, Chia-Hua Chou
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Patent number: 10444779Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.Type: GrantFiled: October 12, 2017Date of Patent: October 15, 2019Assignee: MEDIATEK INC.Inventors: Hao-Yuan Lin, Chia-Hua Chou, Yen-Hsun Hsu
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Patent number: 10326361Abstract: A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result. The low dropout regulator also includes a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result. The low dropout regulator also includes an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.Type: GrantFiled: February 27, 2018Date of Patent: June 18, 2019Assignee: MediaTek Inc.Inventors: Nien-Hui Kung, Chia-Hua Chou, Yen-Hsun Hsu
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Publication number: 20180262105Abstract: A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result. The low dropout regulator also includes a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result. The low dropout regulator also includes an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.Type: ApplicationFiled: February 27, 2018Publication date: September 13, 2018Applicant: MediaTek Inc.Inventors: Nien-Hui Kung, Chia-Hua Chou, Yen-Hsun Hsu
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Publication number: 20180120880Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.Type: ApplicationFiled: October 12, 2017Publication date: May 3, 2018Inventors: Hao-Yuan Lin, Chia-Hua Chou, Yen-Hsun Hsu
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Publication number: 20180120874Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.Type: ApplicationFiled: December 26, 2017Publication date: May 3, 2018Inventors: Chin-Hsun Chen, Hao-Yuan Lin, Chia-Hua Chou
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Patent number: 9886044Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.Type: GrantFiled: February 15, 2016Date of Patent: February 6, 2018Assignee: MEDIATEK INC.Inventors: Chin-Hsun Chen, Hao-Yuan Lin, Chia-Hua Chou
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Publication number: 20170308153Abstract: A power delivery system for a multi-core processor chip includes: a plurality of first power delivery units and a plurality of second power delivery units. The plurality of first power delivery units are coupled to a first power supply device. Each of the first power delivery units is arranged to supply power from the first power supply device to a core of the multi-core processor chip. The plurality of second power delivery units are coupled to a second power supply device. Each of the second power delivery units is arranged to selectively supply power from the second power supply to a core of the multi-core processor chip according to a level of a core voltage required by the core of the multi-core processor chip.Type: ApplicationFiled: February 20, 2017Publication date: October 26, 2017Inventors: Chia-Hua Chou, Yen-Hsun Hsu
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Publication number: 20170038783Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.Type: ApplicationFiled: February 15, 2016Publication date: February 9, 2017Inventors: Chin-Hsun CHEN, Hao-Yuan LIN, Chia-Hua CHOU
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Patent number: 8451150Abstract: A transceiver includes an analog-to-digital converter (ADC) having an embedded processing circuit and an embedded digital-to-analog converting (DAC) unit. The ADC is arranged to convert an analog input signal into a digital output signal during a first operational phase of the transceiver. The embedded processing circuit is arranged to generate a digital code according to the analog input signal and an analog signal. The DAC unit is coupled to the embedded processing circuit, wherein the embedded DAC unit is arranged to convert the digital code into the analog signal during the first operational phase, and is arranged to convert a digital input signal into an analog output signal during a second operational phase of the transceiver.Type: GrantFiled: April 11, 2010Date of Patent: May 28, 2013Assignee: Mediatek Inc.Inventor: Chia-Hua Chou
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Patent number: 8111178Abstract: A capacitor array includes a plurality of capacitor components each having a first node and a second node, and first nodes of the capacitor components are coupled to each other. A calibration method for the capacitor array utilizes a calibration capacitor component to couple the first nodes. Then, the calibration method determines a capacitance indication value regarding the specific capacitor component by coupling different references voltage to a second node of the specific capacitor component and coupling different test voltages to a second node of the calibration capacitor component. Accordingly, the calibration method calibrates the capacitance mismatches of the capacitor array in the digital domain.Type: GrantFiled: November 26, 2009Date of Patent: February 7, 2012Assignee: Mediatek Inc.Inventors: Chieh-Wei Liao, Chia-Hua Chou, Tse-Hsiang Hsu, Wen-Hua Chang
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Publication number: 20110249710Abstract: A transceiver includes an analog-to-digital converter (ADC) having an embedded processing circuit and an embedded digital-to-analog converting (DAC) unit. The ADC is arranged to convert an analog input signal into a digital output signal during a first operational phase of the transceiver. The embedded processing circuit is arranged to generate a digital code according to the analog input signal and an analog signal. The DAC unit is coupled to the embedded processing circuit, wherein the embedded DAC unit is arranged to convert the digital code into the analog signal during the first operational phase, and is arranged to convert a digital input signal into an analog output signal during a second operational phase of the transceiver.Type: ApplicationFiled: April 11, 2010Publication date: October 13, 2011Inventor: Chia-Hua Chou
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Publication number: 20110122006Abstract: A capacitor array includes a plurality of capacitor components each having a first node and a second node, and first nodes of the capacitor components are coupled to each other. A calibration method for the capacitor array utilizes a calibration capacitor component to couple the first nodes. Then, the calibration method determines a capacitance indication value regarding the specific capacitor component by coupling different references voltage to a second node of the specific capacitor component and coupling different test voltages to a second node of the calibration capacitor component. Accordingly, the calibration method calibrates the capacitance mismatches of the capacitor array in the digital domain.Type: ApplicationFiled: November 26, 2009Publication date: May 26, 2011Inventors: Chieh-Wei Liao, Chia-Hua Chou, Tse-Hsiang Hsu, Wen-Hua Chang
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Patent number: 7729214Abstract: An apparatus for obtaining a push-pull signal is disclosed. The apparatus includes: a first amplifier coupled to a first fluctuating signal for utilizing a first gain value to amplify the first fluctuating signal and then outputting a first amplified fluctuating signal; a second amplifier coupled to a second fluctuating signal for utilizing a second gain value to amplify the second fluctuating signal and then outputting a second amplified fluctuating signal; a subtractor electrically connected to the first and second amplifiers for subtracting the second amplified fluctuating signal from the first amplified fluctuating signal to generate the push-pull signal; and a level decision unit electrically connected to the first and second amplifiers for controlling the amplitudes of signals amplified by the first and second amplifiers when the optical disc drive is switched from a first operating mode to a second operating mode.Type: GrantFiled: August 9, 2005Date of Patent: June 1, 2010Assignee: MediaTek Inc.Inventors: Chia-Hua Chou, Chin-Yuan Hu, Ming-Jiou Yu
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Patent number: 7706239Abstract: An apparatus for detecting a pre-pit signal at different laser power intensities of an optical disk drive. The apparatus includes an amplifier for receiving a push-pull signal acquired from an optical disk to generate an adjusted signal, a multiplexer for receiving the push-pull signal and the adjusted signal and selecting the push-pull signal or the adjusted signal as a slicing signal for output according to a power state signal, and a slicer for receiving the slicing signal and slicing the slicing signal according to a slicing level to generate the pre-pit signal. Thus, the apparatus only needs one set of slicer to correctly slice the pre-pit signal.Type: GrantFiled: December 28, 2006Date of Patent: April 27, 2010Assignee: Mediatek Inc.Inventors: Tse-Hsiang Hsu, Chia-Hua Chou