Abstract: A transconductance amplifier circuit with wide input range and high linearity is shown. The transconductance amplifier circuit includes a voltage-to-current circuit having first and second input metal-oxide-semiconductor field-effect transistors (MOSs), first and second output MOSs, a resistor coupled between the drains of the output MOSs, and first and second non-inverting circuits. A differential voltage input is coupled to the gates of the first and second input MOSs. A differential current output is generated at the sources of the first and second output MOSs. The drains of the first and second output MOSs are coupled to the sources of the first and second input MOSs, respectively. The drain of the first input MOS is coupled to the gate of the first output MOS through the first non-inverting circuit, and the drain of the second input MOS is coupled to the gate of the second output MOS through the second non-inverting circuit.

Abstract: A voltage regulator with dynamic voltage and frequency tracking is shown. The voltage regulator has power switches converting an input voltage into an output voltage, a control loop, a voltage comparator, and a target voltage generator. The control loop is coupled to the power switches to control the power switches to perform voltage regulation. The voltage comparator compares the output voltage to the target voltage to generate a first control signal to control the control loop. The target voltage generator generates the target voltage for the voltage comparator based on the frequency difference between the target frequency and the critical-path-related frequency, wherein the critical-path-related frequency depends on the output voltage. The power efficiency and response time are improved.

Abstract: A detection device includes a substrate and a die. The substrate provides a first voltage. The die is disposed adjacent to the substrate. The die includes a plurality of resistor paths, a selection circuit, an ADC (Analog-to-Digital Converter), and a digital circuit. The selection circuit selects one of the resistor paths as a target path. The target path provides a second voltage. The ADC generates a digital signal according to the first voltage and the second voltage. The digital circuit processes the digital signal.

Abstract: An output voltage protection controller includes a comparator circuit and a voltage adjustment circuit. The comparator circuit compares a first voltage signal with a second voltage signal to generate a control signal that controls output voltage protection of a voltage regulator, wherein one of the first voltage signal and the second voltage signal is a feedback voltage derived from an output voltage of the voltage regulator, and another of the first voltage signal and the second voltage signal is a voltage detection threshold. The voltage adjustment circuit injects an offset voltage to the second voltage signal for dynamically adjusting the second voltage signal during a period in which a target regulated voltage level of the output voltage is a constant.

Abstract: The present invention provides a device including a first power delivery channel and a second power delivery channel. The first power delivery channel includes a first voltage regulator, wherein the first voltage regulator is configured to receive a first input voltage to generate a first output signal. The second power delivery channel includes a second voltage regulator and a third voltage regulator, wherein the second voltage regulator receives a second input voltage to generate a second output signal, and the third voltage regulator receives the second output signal to generate a converted second output signal, wherein the first output signal and the converted second output signal are coupled together to a core circuit.

Abstract: A voltage regulator with dynamic voltage and frequency tracking is shown. The voltage regulator has power switches converting an input voltage into an output voltage, a control loop, a voltage comparator, and a target voltage generator. The control loop is coupled to the power switches to control the power switches to perform voltage regulation. The voltage comparator compares the output voltage to the target voltage to generate a first control signal to control the control loop. The target voltage generator generates the target voltage for the voltage comparator based on the frequency difference between the target frequency and the critical-path-related frequency, wherein the critical-path-related frequency depends on the output voltage. The power efficiency and response time are improved.

Abstract: The present invention provides a device including a first power delivery channel and a second power delivery channel. The first power delivery channel includes a first voltage regulator, wherein the first voltage regulator is configured to receive a first input voltage to generate a first output signal. The second power delivery channel includes a second voltage regulator and a third voltage regulator, wherein the second voltage regulator receives a second input voltage to generate a second output signal, and the third voltage regulator receives the second output signal to generate a converted second output signal, wherein the first output signal and the converted second output signal are coupled together to a core circuit.

Abstract: An output voltage protection controller includes a comparator circuit and a voltage adjustment circuit. The comparator circuit compares a first voltage signal with a second voltage signal to generate a control signal that controls output voltage protection of a voltage regulator, wherein one of the first voltage signal and the second voltage signal is a feedback voltage derived from an output voltage of the voltage regulator, and another of the first voltage signal and the second voltage signal is a voltage detection threshold. The voltage adjustment circuit injects an offset voltage to the second voltage signal for dynamically adjusting the second voltage signal during a period in which a target regulated voltage level of the output voltage is a constant.

Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.

Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.

Abstract: A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result. The low dropout regulator also includes a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result. The low dropout regulator also includes an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.

Abstract: A low dropout regulator that produces an output includes a comparison circuit, configured to compare a signal representative of the output and a reference signal to produce a comparison result. The low dropout regulator also includes a loop controller, coupled to the comparison circuit, configured to generate an output circuit control signal based at least in part on the comparison result. The low dropout regulator also includes an output circuit, comprising two or more output stages, configured to adjust a number of active output stages of the two or more output stages based on the output circuit control signal.

Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.

Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.

Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.

Abstract: A power delivery system for a multi-core processor chip includes: a plurality of first power delivery units and a plurality of second power delivery units. The plurality of first power delivery units are coupled to a first power supply device. Each of the first power delivery units is arranged to supply power from the first power supply device to a core of the multi-core processor chip. The plurality of second power delivery units are coupled to a second power supply device. Each of the second power delivery units is arranged to selectively supply power from the second power supply to a core of the multi-core processor chip according to a level of a core voltage required by the core of the multi-core processor chip.

Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.

Abstract: A transceiver includes an analog-to-digital converter (ADC) having an embedded processing circuit and an embedded digital-to-analog converting (DAC) unit. The ADC is arranged to convert an analog input signal into a digital output signal during a first operational phase of the transceiver. The embedded processing circuit is arranged to generate a digital code according to the analog input signal and an analog signal. The DAC unit is coupled to the embedded processing circuit, wherein the embedded DAC unit is arranged to convert the digital code into the analog signal during the first operational phase, and is arranged to convert a digital input signal into an analog output signal during a second operational phase of the transceiver.

Abstract: A capacitor array includes a plurality of capacitor components each having a first node and a second node, and first nodes of the capacitor components are coupled to each other. A calibration method for the capacitor array utilizes a calibration capacitor component to couple the first nodes. Then, the calibration method determines a capacitance indication value regarding the specific capacitor component by coupling different references voltage to a second node of the specific capacitor component and coupling different test voltages to a second node of the calibration capacitor component. Accordingly, the calibration method calibrates the capacitance mismatches of the capacitor array in the digital domain.

Abstract: A transceiver includes an analog-to-digital converter (ADC) having an embedded processing circuit and an embedded digital-to-analog converting (DAC) unit. The ADC is arranged to convert an analog input signal into a digital output signal during a first operational phase of the transceiver. The embedded processing circuit is arranged to generate a digital code according to the analog input signal and an analog signal. The DAC unit is coupled to the embedded processing circuit, wherein the embedded DAC unit is arranged to convert the digital code into the analog signal during the first operational phase, and is arranged to convert a digital input signal into an analog output signal during a second operational phase of the transceiver.