Patents by Inventor Chia-Hua Lu

Chia-Hua Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HVMOS reliability evaluation using bulk resistances as indices
    Patent number: 11955389
    Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
  • Chip package structure
    Patent number: 10622326
    Abstract: A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface, and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the first conductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 14, 2020
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Chen-Tsai Yang, Ko-Chin Yang, Jui-Chang Chuang, Yen-Ting Wu, Chia-Hua Lu
  • CHIP PACKAGE STRUCTURE
    Publication number: 20190057948
    Abstract: A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface, and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the first conductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.
    Type: Application
    Filed: March 5, 2018
    Publication date: February 21, 2019
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Chen-Tsai Yang, Ko-Chin Yang, Jui-Chang Chuang, Yen-Ting Wu, Chia-Hua Lu