Abstract: A netlist of a schematic diagram is generated. The netlist indicates the connectivity of components through connection lines. A normal display mode is provided in which at least a portion of the components are presented on the display, and connection lines corresponding to the components are also displayed. A topology display mode is provided in which the components are presented on the display without the connection lines. The user can switch between the topology display mode and the normal display mode while editing the schematic diagram. Automatic pin assignment and routing of the connection lines is performed according to the netlist, and is based upon grouping similarly classified connection lines. An abstract display mode is provided that presents abstract lines for a selected component, with a single abstract line running between two connected components. The abstract display mode is combinable with the topology display mode.

Abstract: A netlist of a schematic diagram is generated. The netlist indicates the connectivity of components through connection lines. A normal display mode is provided in which at least a portion of the components are presented on the display, and connection lines corresponding to the components are also displayed. A topology display mode is provided in which the components are presented on the display without the connection lines. The user can switch between the topology display mode and the normal display mode while editing the schematic diagram. Automatic pin assignment and routing of the connection lines is performed according to the netlist, and is based upon grouping similarly classified connection lines. An abstract display mode is provided that presents abstract lines for a selected component, with a single abstract line running between two connected components. The abstract display mode is combinable with the topology display mode.

Abstract: Start and stop signals are obtained from a user, with associated start and stop times, as well as circuit simulation results. The simulation results are utilized to determine which of the components in the circuit are active components, which are any components that have an active output signal. Active output signals obtain a state between the start and stop times in response to a state change of the start signal. The user output equipment is utilized to provide the active components and the active output signals to the user. Signal activity is presented in a graphical form that shows the active path circuit, and active value changes that cause output signals to become active. The user may select time values at which signals become active to see in a graphical manner the propagation of a start signal state change through the circuit.

Abstract: HDL code is used to describe a circuit in an HDL code debugger on a computer system. Circuit simulation data is obtained for the circuit, the simulation data being generated according to the HDL code. A circuit execution time is selected, and the simulation data should at least span the circuit execution time. A debugging element is selected, which is a circuit element in the circuit having a debugging state at the circuit execution time according to the simulation data. A target line of HDL code is then presented to a user. The target line of HDL code is the line of code responsible for setting the debugging element into the debugging state at the circuit execution time.

Abstract: Computer-assisted apparatus/method functionally verifies circuit design through automatic generation of verification rules from reusable functional block or IP core using logic simulator and input stimuli. Rule base captures set of design states or scenarios.

Abstract: HDL code is used to describe a circuit in an HDL code debugger on a computer system. Circuit simulation data is obtained for the circuit, the simulation data being generated according to the HDL code. A circuit execution time is selected, and the simulation data should at least span the circuit execution time. A debugging element is selected, which is a circuit element in the circuit having a debugging state at the circuit execution time according to the simulation data. A target line of HDL code is then presented to a user. The target line of HDL code is the line of code responsible for setting the debugging element into the debugging state at the circuit execution time.

Abstract: Hardware description language (HDL)-centered design system and methodology uses HDL specification effectively as master depository for design intent or knowledge. Through network browser, designers conveniently navigate or explore design graphically. Designers selectively review or save design in entirety or portions. Design capture, analysis, and manipulation are based on HDL specification, either directly through text file editing, or indirectly through use of graphical tools.

Abstract: Prior simulation results and model changes are used to shorten re-simulation time in improved design verification methodology, wherein simulator is re-run on design revision. Accelerated incremental simulation scheme boosts engineer design and verification productivity, and facilitates storage of different design revisions and simulation results.