Abstract: A liquid crystal display (LCD) panel including a color filter substrate, a liquid crystal layer and a semiconductor array substrate is provided. The liquid crystal layer is disposed between the two substrates. The semiconductor array substrate disposed at one side of the color filter substrate includes a transparent base, a planar layer, several pixel electrodes and an opaque layer. The pixel electrodes are arranged in an array on the planar layer, which covers the transparent base. Each two adjacent pixel electrodes are spaced by a gap. The opaque layer is disposed in the planar layer, and is located beneath each gap. The opaque layer having an extended portion disposed at two sides thereof is extended towards two sides of each gap to be under part of the pixel electrodes. The opaque layer is at least a half of the planar layer in thickness.

Abstract: A liquid crystal display (LCD) panel including a color filter substrate, a liquid crystal layer and a semiconductor array substrate is provided. The liquid crystal layer is disposed between the two substrates. The semiconductor array substrate disposed at one side of the color filter substrate includes a transparent base, a planar layer, several pixel electrodes and an opaque layer. The pixel electrodes are arranged in an array on the planar layer, which covers the transparent base. Each two adjacent pixel electrodes are spaced by a gap. The opaque layer is disposed in the planar layer, and is located beneath each gap. The opaque layer having an extended portion disposed at two sides thereof is extended towards two sides of each gap to be under part of the pixel electrodes. The opaque layer is at least a half of the planar layer in thickness.

Abstract: Scan lines are formed on a substrate. A patterned dielectric layer and a patterned semiconductor layer are formed to cover portions of the scan lines. A patterned transparent conductive layer and a patterned metal layer are sequentially formed to define data lines, source/drain electrodes, pixel electrodes and etching protecting layers. The etching protective layers cover the exposed scan lines exposed by the patterned dielectric layer and the patterned semiconductor layer, and are electrically connected to the scan lines. A passivation layer is formed, and then the passivation layer over the pixel electrodes and the patterned metal layer of the pixel electrodes are removed to expose the patterned transparent conductive layer. The patterned semiconductor layer over the scan lines between the etching protective layers and the data lines is removed to expose the patterned dielectric layer over the scan lines.

Abstract: Scan lines are formed on a substrate. A patterned dielectric layer and a patterned semiconductor layer are formed to cover portions of the scan lines. A patterned transparent conductive layer and a patterned metal layer are sequentially formed to define data lines, source/drain electrodes, pixel electrodes and etching protecting layers. The etching protective layers cover the exposed scan lines exposed by the patterned dielectric layer and the patterned semiconductor layer, and are electrically connected to the scan lines. A passivation layer is formed, and then the passivation layer over the pixel electrodes and the patterned metal layer of the pixel electrodes are removed to expose the patterned transparent conductive layer. The patterned semiconductor layer over the scan lines between the etching protective layers and the data lines is removed to expose the patterned dielectric layer over the scan lines.