Patents by Inventor Chia-Hui Huang

Chia-Hui Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038571
    Abstract: At least one embodiment, a vacuum chuck includes a moisture gate structure that allows for moisture to escape to reduce an amount of warpage in a workpiece when present on the vacuum chuck. The moisture gate structure includes a base portion that extends laterally outward from a central vacuum portion of the vacuum chuck, and a plurality of protrusions are spaced apart from the central vacuum portion and extend outward from the base portion. End surfaces of the plurality of protrusions contact a backside surface of the workpiece (e.g., a wafer on a carrier) when the workpiece is present on the vacuum chuck. The vacuum chuck may further include one or more guide portions that act as guides such that the workpiece remains properly aligned and within position when present on the vacuum chuck.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Po-Yo SU, Young-Wei LIN, Yu Liang HUANG, Chia-Ching LEE, Chi-Chun PENG, Chen Liang CHANG, Kuo Hui CHANG
  • Publication number: 20240003025
    Abstract: A modified electrode, manufacturing method thereof and use thereof are provided. The manufacturing method includes steps of soaking a copper substrate in a solution to obtain a BiOI/copper(I) iodide, BiOI/copper(I) iodide/metallic bismuth, and copper(I) iodide/metallic bismuth composite modified electrodes by electroless plating method. The obtained electrodes, designated as bismuth-based modified electrode, can be used for the electrohydrodimerization of acrylonitrile to synthesize adiponitrile.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 4, 2024
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Chia-yu Lin, Chia-sheng Su, Chia-hui Yen, Shih-ching Huang, Wei-hsin Lu
  • Publication number: 20230422512
    Abstract: A memory device includes a first memory array including: a plurality of memory strings spaced from each other along a first lateral direction and a second lateral direction, each of the plurality of memory strings including a plurality of memory cells arranged along a vertical direction; and a plurality of first conductive structures extending along the vertical direction; wherein each of the plurality of first conductive structures includes a first portion and a second portion; wherein the first portion extends across the plurality of memory cells of a corresponding pair of the plurality of memory strings along the vertical direction, and the second portion is disposed over the first portion along the vertical direction; and wherein the second portion extends farther than the first portion along at least one of the first or second lateral direction.
    Type: Application
    Filed: July 31, 2023
    Publication date: December 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-En Huang, Meng-Han Lin, Ya-Hui Wu
  • Publication number: 20230402366
    Abstract: A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 14, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Kuan-Kan HU, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN
  • Publication number: 20230387316
    Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Min-Chiang CHUANG, Chia-Cheng CHEN, Chun-Hung WU, Liang-Yin CHEN, Sung-Li WANG, Pinyen LIN, Kuan-Kan HU, Jhih-Rong HUANG, Szu-Hsian LEE, Tsun-Jen CHAN, Cheng-Wei LIAN, Po-Chin CHANG, Chuan-Hui SHEN, Lin-Yu HUANG, Yuting CHENG, Yan-Ming TSAI, Hong-Mao LEE
  • Patent number: 11821847
    Abstract: A wafer backside defect detection method and a wafer backside defect detection apparatus are provided. The wafer backside defect detection method includes the following steps. A peripheral edge area of a wafer backside image that at least one notch is located is cropped off. Adjacent white pixels on the wafer backside image are connected to obtain a plurality of abnormal regions. If a total area of top N of the abnormal regions is more than 10% of an area of the wafer, it is deemed that the wafer has a roughness defect. N is a natural number. If the total area of the top N of the abnormal regions is less than 1% of the area of the wafer and a largest abnormal region of the abnormal regions is longer than a predetermined length, it is deemed that the wafer has a scratch defect.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: November 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hsien Chen, Chia-Feng Hsiao, Chung-Hsuan Wu, Chen-Hui Huang, Nai-Ying Lo, En-Wei Tsui, Yung-Yu Yang, Chen-Hsuan Hung
  • Publication number: 20230367942
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
  • Patent number: 11790145
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20230299168
    Abstract: A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan HU, Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Ken-Yu CHANG, Wei-Yip LOH, Hung-Yi HUANG, Harry CHIEN, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN, Tzu-Pei CHEN, Yuting CHENG
  • Patent number: 11758733
    Abstract: In some aspects of the present disclosure, a memory device includes a first memory array including: a plurality of memory strings spaced from each other along a first lateral direction and a second lateral direction, each of the plurality of memory strings including a plurality of memory cells arranged along a vertical direction; and a plurality of first conductive structures extending along the vertical direction; wherein each of the plurality of first conductive structures includes a first portion and a second portion; wherein the first portion extends across the plurality of memory cells of a corresponding pair of the plurality of memory strings along the vertical direction, and the second portion is disposed over the first portion along the vertical direction; and wherein the second portion extends farther than the first portion along at least one of the first or second lateral direction.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-En Huang, Meng-Han Lin, Ya-Hui Wu
  • Patent number: 11742335
    Abstract: An electronic device is provided. The electronic device includes a driving substrate, a plurality of light-emitting units, and a protective layer. The light-emitting units are electrically connected to the driving substrate. The protective layer covers the light-emitting units, and the protective layer has a Young's modulus less than or equal to 20 MPa.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 29, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Shih-Chang Huang, Chia-Lun Chen, Ming-Hui Chu, Chin-Lung Ting, Chien-Tzu Chu, Hui-Chi Wang
  • Publication number: 20230260993
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Chen-Huang HUANG, Yu-Ling CHENG, Shun-Hui YANG, An Chyi WEI, Chia-Jen CHEN, Shang-Shuo HUANG, Chia-I LIN, Chih-Chang HUNG
  • Patent number: 11725406
    Abstract: The present disclosure provides a spraying system and a using method thereof. The spraying system includes a lifting apparatus and a spraying apparatus. The spraying apparatus connects to the lifting apparatus and includes a stage, a multi-axis transfer mechanism, a spraying component, a driving component, a surface profile detector, and a controlling component. The multi-axis transfer mechanism is disposed on the stage. The spraying component is disposed on the multi-axis transfer mechanism and the stage. The driving component is disposed on the stage and connects to the lifting apparatus. The surface profile detector is disposed on the stage and scans an area to be sprayed to obtain scanning data. The controlling component is disposed on the stage and controls the lifting apparatus, the spraying component, and the driving component according to the scanning data and pre-stored initial data.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: August 15, 2023
    Assignee: KENMEC MECHANICAL ENGINEERING CO., LTD.
    Inventors: Yu-Jen Chen, Chun-Jen Lin, Chia-Hui Huang
  • Publication number: 20230238058
    Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen-Yang Hsueh, Ling-Hsiu Chou, Chih-Yang Hsu
  • Publication number: 20230176638
    Abstract: An electronic device for switching a standby power of a motherboard includes a universal serial bus (USB) connector, electrically connected to the motherboard, configured to connect an external device; a device detecting module, coupled to the USB connector, configured to determine a power control signal according to a voltage level of the USB connector; and an output switching control module, coupled to the device detecting module and the USB connector, configured to determine whether to cut off the standby power provided by the motherboard to the USB connector or not according to the power control signal.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 8, 2023
    Applicant: Wiwynn Corporation
    Inventors: Hao-Chuan Chu, Kuo-Hua Tsai, Che-Wei Lin, Wei-Chih Chen, Po-Lin Huang, Chia-Hui Chen
  • Publication number: 20230166315
    Abstract: A hemming path planning method and a hemming system are provided. The hemming path planning method includes the following steps. An initial contour data of a target is scanned to obtain. A first segment of the hemming path is planned according to the initial contour data. The first segment corresponds to a first bending angle. A second segment of the hemming path is planned according to the initial contour data and an expected springback amount related to the first bending angle. The second segment corresponds to a second bending angle. The first segment and the second segment are combined to obtain a continuous hemming path.
    Type: Application
    Filed: December 26, 2021
    Publication date: June 1, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Yi-Ping Huang, Ya-Hui Tsai, Wei-Chen Li, Bor-Tung Jiang, Chia-Hung Wu, Jen-Yuan Chang
  • Patent number: 11532716
    Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: December 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen Yang Hsueh, Ling Hsiu Chou, Chih-Yang Hsu
  • Publication number: 20220042332
    Abstract: The present disclosure provides a spraying system and a using method thereof. The spraying system includes a lifting apparatus and a spraying apparatus. The spraying apparatus connects to the lifting apparatus and includes a stage, a multi-axis transfer mechanism, a spraying component, a driving component, a surface profile detector, and a controlling component. The multi-axis transfer mechanism is disposed on the stage. The spraying component is disposed on the multi-axis transfer mechanism and the stage. The driving component is disposed on the stage and connects to the lifting apparatus. The surface profile detector is disposed on the stage and scans an area to be sprayed to obtain scanning data. The controlling component is disposed on the stage and controls the lifting apparatus, the spraying component, and the driving component according to the scanning data and pre-stored initial data.
    Type: Application
    Filed: July 16, 2021
    Publication date: February 10, 2022
    Applicant: KENMEC MECHANICAL ENGINEERING CO., LTD.
    Inventors: Yu-Jen CHEN, Chun-Jen LIN, Chia-Hui HUANG
  • Publication number: 20210217866
    Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.
    Type: Application
    Filed: February 18, 2020
    Publication date: July 15, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen Yang Hsueh, Ling Hsiu Chou, Chih-Yang Hsu
  • Patent number: 10668698
    Abstract: Disclosed is an assembly manufacturing method comprising: cutting a prepreg into a prepreg sheet according to a first parameter; moving the prepreg sheet to an assembly arrangement area according to a second parameter; superimposing a metal foil and a plate according to a fourth parameter to form a copper foil set; and assembling the copper foil set and the prepreg sheet according to a third parameter to form an assembly.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 2, 2020
    Assignee: ELITE MATERIAL CO., LTD.
    Inventors: Chia-Hui Huang, Hsing-Lung Li