Patents by Inventor Chia-Hui Liu
Chia-Hui Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111709Abstract: A method for automatically setting addresses suitable for an RS485 system is provided. The RS485 system includes a host device and a plurality of slave devices. The method includes the following stages. The host device confirms that there are no addresses of the slave devices in a database. The slave devices are turned on in sequence. The slave devices calculate their own respective power-on times. The slave device enter an idle state during the period associated with the power-on time. Only one of the slave devices sends the power-on time to the host device when said slave device leaves the idle state. The host device sets the address of said slave device according to the power-on time when said slave device leaves the idle state.Type: ApplicationFiled: July 31, 2023Publication date: April 4, 2024Inventors: Shu-Hui LIU, Chia-Yang LIANG
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Patent number: 11948949Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.Type: GrantFiled: July 15, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
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Publication number: 20240093267Abstract: A high-throughput automated preprocessing method and a system are applied to a nucleic acid preprocessing apparatus including a control system, a sample transfer area, a nucleic acid extraction area, and a reagent setup area. The control system includes a user interface and guides a user to set up on the user interface. In the sample transfer area, the method includes steps of: a user selecting a sampling tube type, a test protocol and an extraction protocol on the user interface, and the control system performing a sample transfer task. In the nucleic acid extraction area, the method includes steps of: the control system performing a nucleic acid extraction task based on the selected extraction protocol. In the reagent setup area, the method includes steps of: the control system performing a reagent deployment task based on the selected test protocol, and the control system performing a nucleic acid transfer task.Type: ApplicationFiled: September 19, 2023Publication date: March 21, 2024Inventors: Wei-Te Hsieh, Chia-Yen Lin, Kuang-An Wang, Keng-Ting Liu, Shu-Hui Huang
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Patent number: 11915977Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: GrantFiled: April 12, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
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Publication number: 20210199652Abstract: The present disclosure provides a test kit for simultaneously detecting a plurality of analytes, in which the test kit includes a lysis solution and a test strip. The lysis solution includes a salt, a surfactant, a stabilizer, and a buffer solution. The test strip includes a sample pad, a conjugation pad, a cellulose membrane, and a water-absorbing pad sequentially arranged on a support plate. The conjugation pad includes a conjugation pad solution and a plurality of antibody-conjugated microspheres, and the antibody-conjugated microspheres recognize plurality of analytes. The test kit of the present disclosure achieves an effect of simultaneously detecting more than or equal to four analytes even though the conjugation pad has a limited capacity of the antibody by preparing the lysis solution with appropriate ingredients and improving a formulation of the solution contained in the test strip.Type: ApplicationFiled: January 4, 2021Publication date: July 1, 2021Applicant: Panion & BF Biotech Inc.Inventors: Chun-Liang Shih, Chia-Hui Liu
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Patent number: 10194530Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.Type: GrantFiled: December 19, 2017Date of Patent: January 29, 2019Assignee: MEDIATEK INC.Inventors: Sheng-Ming Chang, Chia-Hui Liu, Shih-Chieh Lin, Chun-Ping Chen
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Publication number: 20180116051Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.Type: ApplicationFiled: December 19, 2017Publication date: April 26, 2018Inventors: Sheng-Ming Chang, Chia-Hui Liu, Shih-Chieh Lin, Chun-Ping Chen
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Patent number: 9883591Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.Type: GrantFiled: February 14, 2017Date of Patent: January 30, 2018Assignee: MEDIATEK INC.Inventors: Sheng-Ming Chang, Chia-Hui Liu, Shih-Chieh Lin, Chun-Ping Chen
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Publication number: 20170156208Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.Type: ApplicationFiled: February 14, 2017Publication date: June 1, 2017Inventors: Sheng-Ming Chang, Chia-Hui Liu, Shih-Chieh Lin, Chun-Ping Chen
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Patent number: 9609749Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.Type: GrantFiled: September 22, 2015Date of Patent: March 28, 2017Assignee: MEDIATEK INC.Inventors: Sheng-Ming Chang, Chia-Hui Liu, Shih-Chieh Lin, Chun-Ping Chen
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Publication number: 20160143140Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.Type: ApplicationFiled: September 22, 2015Publication date: May 19, 2016Inventors: Sheng-Ming Chang, Chia-Hui Liu, Shih-Chieh Lin, Chun-Ping Chen
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Publication number: 20100283141Abstract: A semiconductor chip package includes a chip; first and second connection pads arranged in a matrix and disposed about the chip, and the first and second connection pads have different bottom surface shapes when viewed from a bottom of the QFN package; bonding pads provided on an active surface of the chip and being electrically connected with corresponding said connection pads through bonding wires; and a package body encapsulating the chip, the bonding wires and an upper portion of each of the connection pads such that a lower portion of each of the connection pads extends outward from a bottom of the package body.Type: ApplicationFiled: May 11, 2009Publication date: November 11, 2010Inventors: Chun-Wei Chang, Tung-Hsien Hsieh, Chia-Hui Liu