Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: A light-emitting element panel, including a temporary storage substrate, an auxiliary pattern layer, multiple adhesive patterns, and multiple light-emitting elements, is provided. The auxiliary pattern layer is disposed on the temporary storage substrate and has multiple openings. The adhesive patterns are respectively disposed in the openings of the auxiliary pattern layer. The light-emitting elements are respectively disposed on the adhesive patterns. A reaction rate of the auxiliary pattern layer to a laser is lower than a reaction rate of the adhesive pattern to the laser. Moreover, another light-emitting element panel is also provided.

Abstract: A pixel array substrate including a substrate, multiple insulation patterns, multiple signal lines, and multiple pixel structures is provided. The insulation patterns are disposed on the substrate, and each has at least one recess structure. The signal lines are respectively disposed on the insulation patterns and are respectively filled in the at least one recess structure of one of the insulation patterns. The pixel structures are disposed on the substrate and are electrically connected to the signal lines. A pixel array substrate further including multiple conductive patterns is also disposed.

Abstract: A display device includes a light emitting element, an adhesive barrier wall and an array substrate. The light emitting element includes a first contact and a second contact disposed on a first surface of the light emitting element. The adhesive barrier wall is disposed on the first surface of the light emitting element and includes a first portion between the first contact and the second contact. The array substrate includes a first pad and a second pad disposed on a second surface of the array substrate. The first contact and the second contact of the light emitting element are respectively connected to the first pad and the second pad.

Abstract: A light emitting diode includes a first semiconductor layer, a second semiconductor layer, a first pad, a second pad, and a protection bump. The first semiconductor layer and the second semiconductor layer are overlapping with each other. An area of a first surface of the first semiconductor layer is larger than an area of a second surface of the second semiconductor layer. The first surface faces the second surface. The first pad is electrically connected to the first semiconductor layer. The second pad is electrically connected to the second semiconductor layer. The protection bump is located between the first pad and the second pad.

Abstract: A pixel array substrate including a substrate, multiple insulation patterns, multiple signal lines, and multiple pixel structures is provided. The insulation patterns are disposed on the substrate, and each has at least one recess structure. The signal lines are respectively disposed on the insulation patterns and are respectively filled in the at least one recess structure of one of the insulation patterns. The pixel structures are disposed on the substrate and are electrically connected to the signal lines. A pixel array substrate further including multiple conductive patterns is also disposed.

Abstract: A marked pixel unit includes at least one active element, a first dielectric layer, a color filter unit, a second dielectric layer, and at least one pixel electrode. The active element includes a source, a gate, and a drain. The first dielectric layer is configured to cover the gate. The color filter unit is disposed above the first dielectric layer, and has an alignment opening. The second dielectric layer is disposed above the active element and the color filter unit, and has a contact hole. The pixel electrode is disposed above the second dielectric layer, and electrically connected to the drain through the contact hole. The contact hole of the second dielectric layer is located outside the alignment opening.

Abstract: A pixel structure includes a scan line, a data line, first and second common lines, first and second sub-pixels, and a color filter layer. The scan line is disposed between the first and second common lines. The first sub-pixel and the second pixel respectively include an active device and a pixel electrode. The pixel electrode of the first sub-pixel is disposed between the scan line and the first common line. The pixel electrode of the second sub-pixel is disposed between the scan line and the second common line. The pixel electrode is connected to the active device through a contact hole. The pixel electrode includes a first side and a second side opposite to each other, wherein the first side of the pixel electrode is adjacent to the scan line, and the contact hole is disposed at an edge of the pixel electrode adjacent to the second side. The color filter layer has an opening exposing the active devices of the first sub-pixel and the second sub-pixel.

Abstract: A marked pixel unit includes at least one active element, a first dielectric layer, a color filter unit, a second dielectric layer, and at least one pixel electrode. The active element includes a source, a gate, and a drain. The first dielectric layer is configured to cover the gate. The color filter unit is disposed above the first dielectric layer, and has an alignment opening. The second dielectric layer is disposed above the active element and the color filter unit, and has a contact hole. The pixel electrode is disposed above the second dielectric layer, and electrically connected to the drain through the contact hole. The contact hole of the second dielectric layer is located outside the alignment opening.

Abstract: A display panel including a first substrate, scan lines, data lines, active devices, color filter patterns, pixel electrodes and a light shielding pattern disposed on the first substrate, a second substrate disposed opposite to the first substrate, a liquid crystal layer disposed between the second substrate and the pixel electrodes and a common electrode disposed on the second substrate is provided. The light shielding pattern is located between two adjacent color filter patterns to shield a gap between the two adjacent color filter patterns. The common electrode has common electrode patterns and a main slit. The common electrode patterns are disposed correspondingly to the pixel electrodes. The main slit is disposed correspondingly to the light shielding pattern.

Abstract: A pixel structure includes a scan line, a data line, first and second common lines, first and second sub-pixels, and a color filter layer. The scan line is disposed between the first and second common lines. The first sub-pixel and the second pixel respectively include an active device and a pixel electrode. The pixel electrode of the first sub-pixel is disposed between the scan line and the first common line. The pixel electrode of the second sub-pixel is disposed between the scan line and the second common line. The pixel electrode is connected to the active device through a contact hole. The pixel electrode includes a first side and a second side opposite to each other, wherein the first side of the pixel electrode is adjacent to the scan line, and the contact hole is disposed at an edge of the pixel electrode adjacent to the second side. The color filter layer has an opening exposing the active devices of the first sub-pixel and the second sub-pixel.

Abstract: A display panel including a first substrate, scan lines, data lines, active devices, color filter patterns, pixel electrodes and a light shielding pattern disposed on the first substrate, a second substrate disposed opposite to the first substrate, a liquid crystal layer disposed between the second substrate and the pixel electrodes and a common electrode disposed on the second substrate is provided. The light shielding pattern is located between two adjacent color filter patterns to shield a gap between the two adjacent color filter patterns. The common electrode has common electrode patterns and a main slit. The common electrode patterns are disposed correspondingly to the pixel electrodes. The main slit is disposed correspondingly to the light shielding pattern.

Abstract: A liquid crystal display (LCD) panel includes an active device array substrate, an opposite substrate, a sealant, a liquid crystal layer, a black matrix, and a plurality of rough structures. The active device array substrate has a display area and a peripheral area surrounding the display area, and the liquid crystal layer and the peripheral area are surrounded by the sealant. The black matrix is disposed between the active device array substrate and the opposite substrate and distributed corresponding to the display area and the peripheral area. The rough structures are disposed on a portion of the black matrix and distributed corresponding to the peripheral area. Surface roughness of the rough structures is greater than surface roughness of the black matrix distributed corresponding to the display area.

Abstract: The present invention provides a polymer stabilization alignment liquid crystal display panel having a plurality of pixel regions defined by plurals of data lines and gate lines. Each pixel region includes a main region and a sub region, and a first pixel electrode and a second pixel electrode correspond to the main region and the sub region respectively, wherein each of the data lines has a first width adjacent to the main display region and a second width adjacent to the sub display region, and the second width is larger than the first width. Each first pixel electrode is separated from the adjacent data line and thereby forming a gap therebetween. Each second pixel electrode partially overlaps the adjacent data line to form an overlap width. Accordingly, the present invention not only can increase the aperture ratio, but also well control the liquid crystal molecules located near the data lines.

Abstract: A thin film transistor (TFT) array includes a substrate, a thin film transistor, a first wall, a transparent electrode and a color resist. The thin film transistor is disposed on the substrate. The first wall is disposed on the substrate and separates a first contact hole from a pixel region on the substrate, wherein the first contact hole exposes a drain electrode of the thin film transistor. The first wall has a first sidewall facing towards the first contact hole and a second sidewall facing towards the pixel region, wherein the slope of the first sidewall is gentler than the slope of the second sidewall. The transparent electrode is electrically connected to the drain electrode of the thin film transistor through the first contact hole. The pixel region is filled with the color resist.

Abstract: A pixel structure including a substrate, a scan line, a first data line, a second data line, a first pixel unit and a second pixel unit is provided. The first pixel unit includes a first active device and a first pixel electrode. The first active device is electrically connected to the scan line and the first data line. The first pixel electrode electrically connected to the first active device and has a plurality of first branches. The first branches outwardly extend from a center of the first pixel unit, and a projection of the first branches are separated from a projection of the adjacent first data line projecting onto the substrate, and the first pixel electrode is apart from the adjacent first data line with a distance. The second pixel unit located between the first data line and the second data line.

Abstract: A thin film transistor (TFT) array includes a substrate, a thin film transistor, a first wall, a transparent electrode and a color resist. The thin film transistor is disposed on the substrate. The first wall is disposed on the substrate and separates a first contact hole from a pixel region on the substrate, wherein the first contact hole exposes a drain electrode of the thin film transistor. The first wall has a first sidewall facing towards the first contact hole and a second sidewall facing towards the pixel region, wherein the slope of the first sidewall is gentler than the slope of the second sidewall. The transparent electrode is electrically connected to the drain electrode of the thin film transistor through the first contact hole. The pixel region is filled with the color resist.

Abstract: A pixel structure including a substrate, a scan line, a first data line, a second data line, a first pixel unit and a second pixel unit is provided. The first pixel unit includes a first active device and a first pixel electrode. The first active device is electrically connected to the scan line and the first data line. The first pixel electrode electrically connected to the first active device and has a plurality of first branches. The first branches outwardly extend from a center of the first pixel unit, and a projection of the first branches are separated from a projection of the adjacent first data line projecting onto the substrate, and the first pixel electrode is apart from the adjacent first data line with a distance. The second pixel unit located between the first data line and the second data line.

Abstract: A thin film transistor (TFT) array includes a substrate, a thin film transistor, a first wall, a transparent electrode and a color resist. The thin film transistor is disposed on the substrate. The first wall is disposed on the substrate and separates a first contact hole from a pixel region on the substrate, wherein the first contact hole exposes a drain electrode of the thin film transistor. The first wall has a first sidewall facing towards the first contact hole and a second sidewall facing towards the pixel region, wherein the slope of the first sidewall is gentler than the slope of the second sidewall. The transparent electrode is electrically connected to the drain electrode of the thin film transistor through the first contact hole. The pixel region is filled with the color resist.

Abstract: A pixel structure including a substrate, a scan line, a first data line and a first pixel unit is provided. The scan line and the first data line are disposed on the substrate. The first pixel unit includes a first active device and a first pixel electrode. The first active device is electrically connected to the scan line and the first data line. The first pixel electrode electrically connected to the first active device has a first stripe pattern and a plurality of first branches. One side of the first stripe pattern is connected to the first branches extended toward the scan line, and the other side of the first stripe pattern is overlapped with the scan line. The overlapped width of the first stripe pattern with the scan line is substantially equal to 40% to 90% of the width of the first stripe pattern.