Patents by Inventor Chia-hung Chen

Chia-hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220375989
    Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.
    Type: Application
    Filed: September 9, 2021
    Publication date: November 24, 2022
    Applicant: Au Optronics Corporation
    Inventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
  • Publication number: 20220376079
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Patent number: 11506923
    Abstract: A display panel includes a substrate, a plurality of standard pixel units, and a plurality of dummy pixel units. A plurality of first conductor patterns and a plurality of shield blocks of a shield pattern layer are arranged in an array above the substrate. Each of the standard pixel units includes one of the first conductor patterns and a first shield block of the shield blocks. The first shield blocks and the first conductor patterns are overlapped, respectively. Each of the dummy pixel units includes a second shield block of the shield blocks. The second shield blocks and the first conductor patterns are not overlapped. A first edge of the substrate is spaced apart from a second edge of one of the standard pixel units adjacent to the dummy pixel units by a first distance. The first distance is within a range from 50 ?m to 3000 ?m.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: November 22, 2022
    Assignee: Au Optronics Corporation
    Inventors: Ping-Hung Shih, Wei-Chieh Sun, Peng-Che Tai, Chia-Heng Chen, Jhih-Ci Chen, Meng-Ting Hsieh
  • Publication number: 20220367632
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Publication number: 20220367565
    Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.
    Type: Application
    Filed: June 11, 2021
    Publication date: November 17, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Cheng-Yi Lin, Tang Chun Weng, Chia-Chang Hsu, Yung Shen Chen, Chia-Hung Lin
  • Publication number: 20220361161
    Abstract: A method for MBS acquisition is provided. The method includes receiving system information from a BS; determining a first CORESET configuration and a second CORESET configuration according to the system information, the first CORESET configuration determining a first set of CORESETs scheduling at least one MCCH, the second CORESET configuration determining a second set of CORESETs scheduling a plurality of MTCHs; receiving an MCCH message on the at least one MCCH provided through a first beam of a plurality of beams associated with the BS; and determining, according to the second CORESET configuration and the MCCH message, a plurality of MBS-specific CORESET groups in the second set of CORESETs, wherein each of the plurality of MBS-specific CORESET groups corresponds to a respective MBS session and includes at least two CORESETs configured to be provided through at least two different beams of the plurality of beams. A UE using the method is also provided.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 10, 2022
    Inventors: CHIA-HUNG WEI, HAI-HAN WANG, HUNG-CHEN CHEN, HENG-LI CHIN
  • Publication number: 20220354736
    Abstract: A medical vast and using method thereof. The medical vest has a clothe capable of surrounding the chest of a user's body, one or more vibration devices located in the clothe respectively and a motion sensor located in the clothe. Hence, when a user wears the medical vest and/or when the user actives one or more vibration devices to apply a net vibration force to the users' chest, the motion sensor may detect the user's real posture and/or both the vibration intensity and/or the vibration frequency of the vibration force applied to the user's chest. Accordingly, the user may adjust the vibration intensity and/or the vibration frequency of one or more vibration devices, also may adjust how the clothe is worn on the user's chest.
    Type: Application
    Filed: June 17, 2020
    Publication date: November 10, 2022
    Inventor: Chia-Hung CHEN
  • Publication number: 20220359158
    Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Sheng-Liang Pan, Bing-Hung Chen, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang, Jack Kuo-Ping Kuo
  • Patent number: 11495501
    Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Patent number: 11495681
    Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: November 8, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Po Hsiung, Ching-Chung Yang, Shan-Shi Huang, Shin-Hung Li, Nien-Chung Li, Wen-Fang Lee, Chiu-Te Lee, Chih-Kai Hsu, Chun-Ya Chiu, Chin-Hung Chen, Chia-Jung Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • Publication number: 20220353901
    Abstract: A method of uplink transmission for a user equipment (UE) is disclosed. The method comprises receiving, from a base station (BS), a threshold; determining at least one uplink grant according to the threshold; performing a payload transmission on the at least one uplink grant while the UE is in an RRC inactive state; and not transmitting only padding bits for the payload transmission on the uplink grant.
    Type: Application
    Filed: September 24, 2020
    Publication date: November 3, 2022
    Inventors: CHIA-HUNG LIN, HUNG-CHEN CHEN, CHIA-HAO YU
  • Patent number: 11488837
    Abstract: A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: November 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Jung Hsu, Chun Yu Chen, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • Publication number: 20220344133
    Abstract: A method for forming a layer includes following operations. A workpiece is received in an apparatus for deposition. The apparatus for deposition includes a chamber, a pedestal disposed in the chamber to accommodate the workpiece, and a ring disposed on the pedestal. The ring includes a ring body having a first top surface and a second top surface and a barrier structure disposed between the first top surface and the second top surface. A vertical distance is defined by a top surface of the barrier structure and a top surface of the workpiece. The vertical distance is between approximately 0 mm and approximately 50 mm. A target disposed in the apparatus for deposition is sputtered. A sputtered material is deposited onto a top surface of the workpiece to form a layer. The barrier structure alters an electrical density distribution during the depositing the sputter material.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: HSIN-LIANG CHEN, WEN-CHIH WANG, CHIA-HUNG LIAO, CHENG-CHIEH CHEN, YI-MING YEH, HUNG-TING LIN, YUNG-YAO LEE
  • Publication number: 20220344579
    Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
    Type: Application
    Filed: May 13, 2021
    Publication date: October 27, 2022
    Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
  • Patent number: 11482717
    Abstract: A dehydrogenation method for hydrogen storage materials, which is executed by a fuel cell system. The fuel cell system includes a hydrogen storage material tank, a heating unit, a fuel cell, a pump, a water thermal management unit and a heat recovery unit. The described dehydrogenation method utilizes the heating unit and the heat recovery unit to provide thermal energy to the hydrogen storage material tank, so that hydrogen storage material is heated to the dehydrogenation temperature. The pump extracts hydrogen from the hydrogen storage material tank, so that the hydrogen storage material is under negative pressure (i.e. H2 absolute pressure below 1 atm), according to which the hydrogen storage material is dehydrogenated, and the dehydrogenation efficiency and the amount of hydrogen release are improved. The method n can reduce the dehydrogenation temperature of the hydrogen storage material, and reduce the thermal energy consumption for heating the hydrogen storage material.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 25, 2022
    Inventors: Chia-Chieh Shen, Shih-Hung Chan, Fang-Bor Weng, Ho Chun Cheung, Yi-Hsuan Lin, Mei-Chin Chen, Jyun-Wei Chen, Ya-Che Wu, Han-Wen Liu, Kuan-Lin Chen, Jin-Xun Zhang
  • Publication number: 20220330663
    Abstract: An apparatus for buffing a shoe part includes a housing adapted to be articulated around at least a portion of the footwear part. A rotating spindle is positioned in the housing and has a buffing surface for engagement with the footwear part. A carriage is slideably connected to the housing and holds the spindle such that the buffing surface can be moved closer to and further away from the footwear part. An actuator is in the housing and in contact with the carriage. The actuator applies force to the carriage to increase the force of the buffing surface onto the footwear part. A biasing member is in the housing and in contact with the carriage. The biasing member exerts force onto the carriage in a direction opposite the force exerted by the actuator.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Dragan Jurkovic, Shih-Yuan Wu Wu, Chia-Wei Chang, Wen-Ruei Chang, Chien-Chun Chen, Chang-Chu Liao, Chia-Hung Lin
  • Publication number: 20220336612
    Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.
    Type: Application
    Filed: December 10, 2021
    Publication date: October 20, 2022
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG, Chia-Pin LIN, Wei-Yang LEE, Yen-Sheng LU
  • Publication number: 20220328961
    Abstract: An antenna module includes a first, a second, a third radiators, and a ground radiator. The first radiator includes a first section and a second section. The second radiator is connected to the first radiator, and includes a third section and a fourth section connected to each other. The fourth section includes a feed end. The third radiator is connected to the third section of the second radiator. The ground radiator is connected to the third radiator. The first, the second, the third, and the ground radiator are sequentially connected in a bent manner to form a stepped shape. The first section of the first radiator and the fourth section of the second radiator jointly resonate at a low frequency band, and the second section of the first radiator, the second radiator, the third radiator, and the ground radiator jointly resonate at a high frequency band.
    Type: Application
    Filed: February 21, 2022
    Publication date: October 13, 2022
    Applicant: PEGATRON CORPORATION
    Inventors: Cheng-Hsiung Wu, Chien-Yi Wu, Chao-Hsu Wu, Hau Yuen Tan, Ching-Hsiang Ko, Shih-Keng Huang, Chia-Hung Chen
  • Publication number: 20220328360
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
  • Patent number: 11469474
    Abstract: A battery assembly includes a battery holding unit and a battery unit removably held by the battery holding unit. The battery unit includes a battery, a first engaging portion, and a second engaging portion. The battery holding unit includes a holding member selectively engaged with the first engaging portion or the second engaging portion to hold the battery unit at a first position or a second position. When the holding member and the first engaging portion relatively move away from each other along a disengagement direction, the battery unit moves along a detachment direction from the first position to the second position at which the holding member engages with the second engaging portion, and the second engaging portion is allowed to move to disengage from the holding member, so that the battery unit moves again along the detachment direction to be removed from the battery holding unit.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 11, 2022
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Chia-Hung Liu, Chien-Hung Chen