Patents by Inventor Chia-Hung S. Kuo
Chia-Hung S. Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107031Abstract: An example apparatus determines a size of a dirty region of a video frame; after the size of the dirty region satisfies a threshold: encode the dirty region of the video frame to generate an encoded dirty region; and cause storing of the dirty region in the cache; and after the size of the dirty region does not satisfy the threshold: cause storing of the video frame in a volatile memory that is separate from the cache; and encode the video frame via inter-encoding to generate an encoded video frame.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Stanley Baran, Jason Tanner, Venkateshan Udhayan, Chia-Hung S. Kuo
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Publication number: 20240048727Abstract: A computer-implemented method of video coding comprises receiving at least one frame of a video sequence of an interactive application interface associated with at least one asset displayable on the interface in response to a user action related to the interface. The method includes encoding the at least one frame. The method also includes transmitting the at least one asset and the encoded at least one frame to a remote device. The transmitting operation refers to performing the transmitting regardless of whether a request to display the at least one asset exists. The asset can be a non-persistent asset on the frame only while a user performs a continuous action or maintains a cursor at a specific place on the interface. The asset also can be a persistent asset on the frame in response to a first action and is removed from the display in response to a second action.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Applicant: Intel CorporationInventors: Jason Tanner, Stanley Baran, Kristoffer Fleming, Chia-Hung S. Kuo, Sankar Radhakrishnan, Venkateshan Udhayan
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Publication number: 20230086149Abstract: Some embodiments include apparatuses and electrical models associated with the apparatus. One of the apparatuses includes a power control unit to monitor a power state of the apparatus for entry into a standby mode. The apparatus can include a two-level memory (2LM) hardware accelerator to, responsive to a notification from the power control unit of entry into the standby mode, flush dynamic random access memory (DRAM) content from a first memory part to a second memory part. The apparatus can include processing circuitry to determine memory utilization and move memory from a first memory portion to a second memory portion responsive to memory utilization exceeding a threshold. Other methods systems and apparatuses are described.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Chia-Hung S. Kuo, Deepak Gandiga Shivakumar, Anoop Mukker, Arik Gihon, Zvika Greenfield, Asaf Rubinstein, Leo Aqrabawi
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Patent number: 11500444Abstract: A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.Type: GrantFiled: May 8, 2020Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Leo Aqrabawi, Chia-hung S. Kuo, James G. Hermerding, II, Premanand Sakarda, Bijan Arbab, Kelan Silvester
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Publication number: 20220335209Abstract: Systems, apparatus, articles of manufacture, and methods to generate digitized handwriting with user style adaptations are disclosed. An example apparatus includes at least one memory, and processor circuitry to train a machine learning model to generate a first digitized handwriting sequence based on a stored handwriting sample. To train the machine learning model, the processor circuitry is to cause a parameterization of a first portion of the machine learning model; and cause a reparameterization of a second portion of the machine learning model. The processor circuitry to re-train the trained machine learning model to generate a second digitized handwriting sequence based on a user handwriting sample.Type: ApplicationFiled: June 27, 2022Publication date: October 20, 2022Inventors: Chia-Hung S. Kuo, Sherine Abdelhak, Tamoghna Ghosh, Vijayalaxmi Patil
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Publication number: 20220334638Abstract: Systems, apparatus, articles of manufacture, and methods for eye gaze correction in camera image streams are disclosed. An example apparatus disclosed herein includes timing circuitry to calculate a duration of time for which an eye gaze of a first user of a video conference is directed toward a second user of the video conference, the second user presented as an image via a video conference interface, the video conference interface presented by a display of an electronic device, and social feedback control circuitry to select an eye gaze time threshold based on content associated with the video conference interface, and in response to the duration satisfying the eye gaze time threshold, cause an alert to be presented on the display with the video conference interface.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Glen J. Anderson, Chia-Hung S. Kuo, Sangeeta Manepalli, Passant Karunaratne
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Publication number: 20220321622Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate multi participant conversation. An example apparatus to control interruptions includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to detect first audio from a first user device, detect second audio from a second user device, determine the second detected audio is an interruption attempt in response to a start of the second detected audio being received during a presentation time of the first detected audio, render an interruption notification to the second user device, and control a manner of rendering the second detected audio based on interruption control settings.Type: ApplicationFiled: June 23, 2022Publication date: October 6, 2022Inventors: Chia-Hung S. Kuo, Stanley Baran, Atsuo Kuwahara, David Browning
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Publication number: 20220188016Abstract: An example apparatus includes processor circuitry to execute instructions to determine memory usage data associated with a user profile, determine an address hashing policy based on the memory usage data, and determine power states of memory channels based on the address hashing policy.Type: ApplicationFiled: December 21, 2021Publication date: June 16, 2022Inventors: Jianwei Dai, Virendra Vikramsinh Adsure, Taeyoung Kim, Chia-Hung S. Kuo, Deepak Gandiga Shivakumar, Amir Ali Radjai, Deepak Samuel Kirubakaran, Jianfang Zhu, Ivan Chen
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Publication number: 20220114136Abstract: Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.Type: ApplicationFiled: December 21, 2021Publication date: April 14, 2022Inventors: Jianfang Zhu, Ivan Chen, Barnes Cooper, Jianwei Dai, Martin Dixon, Kristoffer Fleming, Mark Gallina, Duncan Glendinning, Deepak Samuel Kirubakaran, Chia-Hung S. Kuo, Yifan Li, Adam Norman, Michael Rosenzweig, Kai P Wang, Jin Yan, Virendra Vikramsinh Adsure
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Publication number: 20220091644Abstract: A first circuit to receive from a sensor a thermal condition of a voltage regulator while circuitry comprising the voltage regulator is to regulate delivery of power to a power domain having first and second components. The circuitry is to control a first power consumption rate of the first component based on a first parameter and control a second power consumption rate of the second component based on a second parameter. The first circuit monitors the thermal condition and generates an evaluation result based on a test criterion. A second circuit receives from the first circuit a signal based on the evaluation result. Based on the signal, the second circuit is to signal the circuitry to change the first parameter. An amount of any change to the second parameter based on the evaluation result is different than an amount of change to the first parameter based on the evaluation result.Type: ApplicationFiled: December 2, 2021Publication date: March 24, 2022Applicant: Intel CorporationInventors: Samantha Rao, Zhongsheng Wang, Somvir Singh Dahiya, Chee Lim Nge, Siang Yeong Tan, Chia-Hung S. Kuo
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Patent number: 11237610Abstract: Described are mechanisms and methods for reducing CPU power upon interruption of a supplied power. In some embodiments, an apparatus may comprise an input to receive an indicator that a supply voltage to a computer system has been interrupted. The apparatus may comprise an output to provide an indicator to reduce a processor power consumption level. The apparatus may also comprise a circuitry to establish the indicator to reduce the processor power level based upon the indicator that the supply voltage to the computer system has been interrupted.Type: GrantFiled: November 20, 2019Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Chia-Hung S. Kuo, Philip Lehwalder, Arik Gihon
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Publication number: 20210349519Abstract: A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.Type: ApplicationFiled: May 8, 2020Publication date: November 11, 2021Applicant: Intel CorporationInventors: Leo Aqrabawi, Chia-hung S. Kuo, James G. Hermerding II, Premanand Sakarda, Bijan Arbab, Kelan Silvester
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Publication number: 20210325956Abstract: Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Inventors: Virendra Vikramsinh ADSURE, Chia-Hung S. KUO, Robert J. ROYER, JR., Deepak GANDIGA SHIVAKUMAR
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Patent number: 11144467Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.Type: GrantFiled: May 17, 2019Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Yanru Li, Ali Taha, Chia-Hung S. Kuo
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Publication number: 20210149469Abstract: Described are mechanisms and methods for reducing CPU power upon interruption of a supplied power. In some embodiments, an apparatus may comprise an input to receive an indicator that a supply voltage to a computer system has been interrupted. The apparatus may comprise an output to provide an indicator to reduce a processor power consumption level. The apparatus may also comprise a circuitry to establish the indicator to reduce the processor power level based upon the indicator that the supply voltage to the computer system has been interrupted.Type: ApplicationFiled: November 20, 2019Publication date: May 20, 2021Applicant: Intel CorporationInventors: Chia-Hung S. Kuo, Philip Lehwalder, Arik Gihon
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Patent number: 10949356Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.Type: GrantFiled: June 14, 2019Date of Patent: March 16, 2021Assignee: Intel CorporationInventors: James A. Boyd, Robert J. Royer, Jr., Lily P. Looi, Gary C. Chow, Zvika Greenfield, Chia-Hung S. Kuo, Dale J. Juenemann
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Patent number: 10860522Abstract: A method and system for manages mapping of universal serial bus (USB) connectors to a plurality of USB host controllers. The method determines an enumeration of USB connectors in a system, identifying USB host controllers in the system, generating a grouping for a USB connector with USB host controllers, and configures USB routing in the system to map the USB connector with the USB host controllers according to the grouping.Type: GrantFiled: May 19, 2017Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Tin-Cheung Kung, Chia-Hung S. Kuo, Nivedita Aggarwal
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Patent number: 10860789Abstract: Embodiments may include systems and methods for managing multiple ports of a computing interface. A computing device may include a connector with a power port and a data port. A connector manager may identify whether a port partner is coupled to the connector, identify an inquiry related to a status of the connector, where the inquiry may be received from a BIOS of the computing device. In addition, the connector manager may generate an indication of the status of the connector, and further transmit the indication of the status of the connector to the BIOS. A BIOS may identify that a data device coupled to the connector through a port partner is to be initialized, and further transmit to a connector manager an inquiry related to a status of the connector, before initializing the data device. Other embodiments may be described and/or claimed.Type: GrantFiled: June 23, 2017Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Vijaykumar B. Kadgi, Venkataramani Gopalakrishnan, Basavaraj B. Astekar, Chia-Hung S. Kuo, Nivedita Aggarwal
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Patent number: 10585464Abstract: Systems, apparatuses and methods may provide for a thermal protection apparatus comprising a substrate including surfaces defining one or more channels and an array of openings adjacent to the one or more channels and an outer layer coupled to the substrate. The outer layer may include a plurality of opaque elastic regions positioned adjacent to the array of openings. Additionally, a fluid may be positioned within the one or more channels. In one example, the plurality of opaque elastic regions are expandable to become protrusions including one or more of a rectangular shape, a donut shape or a dome shape.Type: GrantFiled: March 28, 2016Date of Patent: March 10, 2020Assignee: Intel CorporationInventors: Hong W. Wong, Wah Yiu Kwong, Cheong W. Wong, Vivek M. Paranjape, Chia-Hung S. Kuo
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Publication number: 20190303300Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.Type: ApplicationFiled: June 14, 2019Publication date: October 3, 2019Inventors: James A. BOYD, Robert J. ROYER, JR., Lily P. LOOI, Gary C. CHOW, Zvika GREENFIELD, Chia-Hung S. KUO, Dale J. JUENEMANN