Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.

Abstract: A protective film with an antibacterial property for manufactured products and for constantly-handled objects and equipment is formed by solidifying a water-based slurry. The water-based slurry includes 60 parts to 80 parts by weight of a water-based polyurethane, 1 part to 1.5 parts by weight of a dispersant, 1 part to 10 parts by weight of an antibacterial agent, 0.5 parts by weight of a defoamer, and 9 parts to 32 parts by weight of water. The protective film can be sprayed, applied in a dip, or brushed-on, having good adhesion to a surface but is peelable.

Abstract: A water-based protective film which is largely immune to static electricity includes 60 to 70 parts of a water-based polyurethane by weight, 12 to 17 parts of an emulsion dispersant by weight, 3 to 8 parts of an antistatic agent by weight, and 10 to 20 parts of water by weight. A preparation method of the water-based protective film is also disclosed, the water-based protective film, which is in a form of slurry before drying, can be applied to an object surface by spraying, by immersion, or by brushing.

Abstract: A composition for preparing polyamide powders, includes polyamide granules, a nucleating agent and an organic solvent having a boiling point ranging from 190° C. to 209° C. The weight ratio of the polyamide granules to the organic solvent ranges from 0.11 to saturation solubility of the polyamide granules is the organic solvent, and the weight ratio of the polyamide granules to the nucleating agent is 100:1.

Abstract: A method of preparing polyamide (PA) powders includes the steps of: heating a composition including PA granules, a nucleating agent and an organic solvent under normal pressure to T1 not lower than melting point (Tm) of PA granules and maintaining at T1 to dissolve PA granules; cooling the heated composition to T2 to nucleate the dissolved PA granules and maintaining at T2 to crystallize, where 15° C.?Tm?T2?33° C.; cooling the crystallization product to precipitate PA; and washing the precipitated product to remove the organic solvent. The weight ratio of PA granules to the nucleating agent is 100:1, and the weight ratio of PA granules to the organic solvent ranges from 0.11 to saturation solubility of PA granules in the organic solvent.

Abstract: A method of preparing polyamide (PA) powders includes the steps of: heating a composition including PA granules, a nucleating agent and an organic solvent under normal pressure to T1 not lower than melting point (Tm) of PA granules and maintaining at T1 to dissolve PA granules; cooling the heated composition to T2 to nucleate the dissolved PA granules and maintaining at T2 to crystallize, where 15° C.?Tm?T2?33° C.; cooling the crystallization product to precipitate PA; and washing the precipitated product to remove the organic solvent. The weight ratio of PA granules to the nucleating agent is 100:1, and the weight ratio of PA granules to the organic solvent ranges from 0.11 to saturation solubility of PA granules in the organic solvent.

Abstract: A transistor having a bottom dielectric layer, a first layer, a second layer, a top dielectric layer, and a gate electrode. The first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer. The first layer, the second layer, and the top dielectric layer are configured to form a hole wire in the first layer. The gate electrode is over a portion of the hole wire and divides the top dielectric layer into a source contact and a drain contact.

Abstract: A transistor having a bottom dielectric layer, a first layer, a second layer, a top dielectric layer, and a gate electrode. The first layer and the second layer form a composite quantum well between the bottom dielectric layer and the top dielectric layer. The first layer, the second layer, and the top dielectric layer are configured to form a hole wire in the first layer. The gate electrode is over a portion of the hole wire and divides the top dielectric layer into a source contact and a drain contact.

Abstract: A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; wherein a portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer. A method of etching comprising the steps of: providing a heterostructure; providing an etchant solution comprising acetic acid, hydrogen peroxide, and water; and contacting the etchant solution to the heterostructure to etch the heterostructure.

Abstract: A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; wherein a portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer. A method of etching comprising the steps of: providing a heterostructure; providing an etchant solution comprising acetic acid, hydrogen peroxide, and water; and contacting the etchant solution to the heterostructure to etch the heterostructure.

Abstract: A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; wherein a portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer. A method of etching comprising the steps of: providing a heterostructure; providing an etchant solution comprising acetic acid, hydrogen peroxide, and water; and contacting the etchant solution to the heterostructure to etch the heterostructure.

Abstract: The present invention discloses both an n+ and a p+ unipolar, three-terminal, resonant-tunneling transistor that can be operated as a hot-electron transistor or a field effect transistor at temperatures at least as low as 77 degree Kelvin. The doped first terminal (collector or gate) is made of 3D metal or semiconductor material. An undoped insulating barrier is deposited on the first terminal. The doped electrically-contacted second terminal (emitter or source), made of a 2D semiconductor material, is deposited on the insulating barrier. An undoped double-barrier resonant-tunneling structure is deposited on the second terminal. A doped third terminal, made of 3D metal or semiconductor material, is deposited on a portion of the double-barrier resonant-tunneling structure. A doped tunneling-contact, made of 3D metal or semiconductor material, is deposited on the double-barrier resonant-tunneling structure so that the tunneling contact is isolated from the third terminal.