Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.

Abstract: A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.

Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: A processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a first load instruction included in a plurality of load instructions to generate a first decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instructions use a same register. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the first load instruction according to the first decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instructions use the same register, the data buffer is configured to store the first address generated from the address generator, and store data requested by the first load instruction according to the first address.

Abstract: A margin assessment method is provided. Under cooperation of harmonic generation microscopy (HGM) and a deep learning method, the margin assessment method can instantaneously and digitally determine whether a 3D image group generated by an HGM imaging system is a malignant tumor or the surrounding normal skin, so as to assist in determining margins of a lesion.

Abstract: The present disclosure provides a checker and a checking method for a processor circuit. The checking method includes: determining whether a data cache send a data refill request under a branch prediction executing status for obtaining a first result; determining whether data requested by the data refill request is written into a register and calculated under the branch prediction executing status for obtaining a second result; and determining whether the processor circuit has a vulnerability according to the first result and the second result.

Abstract: A margin assessment method is provided. Under cooperation of harmonic generation microscopy (HGM) and a deep learning method, the margin assessment method can instantaneously and digitally determine whether a 3D image group generated by an HGM imaging system is a malignant tumor or the surrounding normal skin, so as to assist in determining margins of a lesion.

Abstract: A processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a first load instruction included in a plurality of load instructions to generate a first decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instructions use a same register. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the first load instruction according to the first decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instructions use the same register, the data buffer is configured to store the first address generated from the address generator, and store data requested by the first load instruction according to the first address.

Abstract: A pipeline computer system includes a processor circuit and a memory circuit. The processor circuit is configured to obtain a first target address of a first branch instruction and a second address of a first prediction instruction according to a first address of the first branch instruction before the first branch instruction is executed, and sequentially prefetch a first instruction corresponding to the first target address and the first prediction instruction when a prediction result of the first branch instruction is branch-taken, in which an execution of the first instruction is followed by an execution of the first prediction instruction. The memory circuit is configured to store the first instruction and the first prediction instruction.

Abstract: The present invention discloses a counting circuit of a performance monitor unit, capable of preventing a cycle counter from being suspended due to the occurrence of an overflow. An embodiment of the counting circuit includes a cycle counter and an event counter. The cycle counter starts counting from a beginning number according to a cycle of a clock signal during enablement duration, and when a count of the cycle counter reaches a count maximum of the cycle counter during the enablement duration, the cycle counter changes a level of a trigger signal and then counts from the beginning number again. The event counter counts according to change of the level of the trigger signal. Accordingly, the counting circuit is operable to obtain a total cycle number of the clock signal in the enablement duration according to the count of the cycle counter and a count of the event counter.

Abstract: This invention discloses a floating-point number operation circuit and a method thereof. The floating-point number operation circuit is configured to perform a fused multiplication and accumulation (fused mac) operation or a multiplication and accumulation (mac) operation on a first operand, a second operand, and a third operand, or perform a multiplication operation on the first operand and the second operand. The floating-point number operation circuit includes two rounding circuits, a multiplication circuit, a selection circuit, a control circuit, and an addition circuit. The control circuit controls the scheduling of various operations and the use of resources on each calculation path.

Abstract: The present invention discloses a counting circuit of a performance monitor unit, capable of preventing a cycle counter from being suspended due to the occurrence of an overflow. An embodiment of the counting circuit includes a cycle counter and an event counter. The cycle counter starts counting from a beginning number according to a cycle of a clock signal during enablement duration, and when a count of the cycle counter reaches a count maximum of the cycle counter during the enablement duration, the cycle counter changes a level of a trigger signal and then counts from the beginning number again. The event counter counts according to change of the level of the trigger signal. Accordingly, the counting circuit is operable to obtain a total cycle number of the clock signal in the enablement duration according to the count of the cycle counter and a count of the event counter.

Abstract: This invention discloses a floating-point number operation circuit and a method thereof. The floating-point number operation circuit is configured to perform a fused multiplication and accumulation (fused mac) operation or a multiplication and accumulation (mac) operation on a first operand, a second operand, and a third operand, or perform a multiplication operation on the first operand and the second operand. The floating-point number operation circuit includes two rounding circuits, a multiplication circuit, a selection circuit, a control circuit, and an addition circuit. The control circuit controls the scheduling of various operations and the use of resources on each calculation path to simplify the circuit and improve the performance of the processor.

Abstract: Multiplexers are basic components widely used in VLSI designs. Switching activities of a multiplexer are one of the most important factors of power consumption. A multiplexer may have some sub-multiplexers. An extra dynamic controller is applied in the present invention to reconfigure control signals for decreasing switching activities of the composed sub-multiplexers. Thus, the power consumption of the multiplexer is reduced to achieve higher power efficiency.

Abstract: Multiplexers are basic components widely used in VLSI designs. Switching activities of a multiplexer are one of the most important factors of power consumption. A multiplexer may have some sub-multiplexers. An extra dynamic controller is applied in the present invention to reconfigure control signals for decreasing switching activities of the composed sub-multiplexers. Thus, the power consumption of the multiplexer is reduced to achieve higher power efficiency.

Abstract: The present invention is an integration method and structure of wood material and a plastic material. The method includes obtaining at least one piece of wood material, forming the wood material to a pre-determined shape, placing the wood material inside a plastic injection mold; forming a plastic base inside the wood material by use of a plastic composition in the plastic injection mold. The plastic composition of the plastic base permeates into fibers of the wood material, thus, the two materials are integrated into one piece. The wood material uses plastic base as durable support. The pre-determined shape of the wood material and the area of the plastic base displays the texture of natural wood of the wood material. Thus, the wood and plastic materials integrate perfectly to meet product demand.