Patents by Inventor Chia-Jen Cheng
Chia-Jen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105642Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
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Patent number: 11942464Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.Type: GrantFiled: July 19, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20240088062Abstract: A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.Type: ApplicationFiled: November 23, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
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Publication number: 20230087397Abstract: A personnel tracking and disinfecting system is applied to a place and includes recognition devices, at least one disinfecting device, storage and central controller. The central controller is configured to: control the recognition devices to recognize the person in the place; determine the position of the person in the place by cooperating with the recognition devices; activate the disinfecting device in the main area to disinfect the person in the main area, generate a disinfecting record based on recognition result generated by the recognition device in the main area, and store the disinfecting record in the storage; and determine whether the person in the extended area has the disinfecting record based on recognition result generated by the recognition device in the extended area.Type: ApplicationFiled: December 27, 2021Publication date: March 23, 2023Inventors: Chia-Jen CHENG, Chih-Wei TSAI, Chih-Hsien WANG
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Patent number: 10157839Abstract: An interconnect structure includes a first substrate including a first surface, a second surface opposite to the first surface, a cavity extended through the first substrate, and a first recess extended from the second surface towards the first surface; a second substrate disposed opposite to the second surface of the first substrate; an electronic device disposed within the cavity; a first polymeric layer disposed over the first surface and within the cavity of the first substrate; and a second polymeric layer disposed between the first substrate and the second substrate and within the first recess.Type: GrantFiled: December 14, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Jen Cheng, Hsiu-Mei Yu
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Publication number: 20180342456Abstract: An interconnect structure includes a first substrate including a first surface, a second surface opposite to the first surface, a cavity extended through the first substrate, and a first recess extended from the second surface towards the first surface; a second substrate disposed opposite to the second surface of the first substrate; an electronic device disposed within the cavity; a first polymeric layer disposed over the first surface and within the cavity of the first substrate; and a second polymeric layer disposed between the first substrate and the second substrate and within the first recess.Type: ApplicationFiled: December 14, 2017Publication date: November 29, 2018Inventors: CHIA-JEN CHENG, HSIU-MEI YU
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Patent number: 9515038Abstract: A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.Type: GrantFiled: May 5, 2015Date of Patent: December 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Chia-Jen Cheng, Hsiu-Mei Yu
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Publication number: 20150235976Abstract: A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.Type: ApplicationFiled: May 5, 2015Publication date: August 20, 2015Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Chia-Jen Cheng, Hsiu-Mei Yu
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Patent number: 9087882Abstract: A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.Type: GrantFiled: December 27, 2013Date of Patent: July 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Chia-Jen Cheng, Hsiu-Mei Yu
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Publication number: 20140113447Abstract: A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.Type: ApplicationFiled: December 27, 2013Publication date: April 24, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Chia-Jen Cheng, Hsiu-Mei Yu
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Patent number: 8669658Abstract: A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.Type: GrantFiled: July 24, 2007Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mon-Chin Tsai, Hsiu-Mei Yo, Chien-Min Lin, Chia-Jen Cheng, Li-Hsin Tseng
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Patent number: 8640569Abstract: A freewheel structure includes a wheel frame and at least one weight block. The wheel frame has a central axle portion and a flange portion around an outer edge thereof. The axle portion is for insertion of an axle member. The weight block is selectively located between the axle portion and the flange portion, so that the weight block has a certain distance relative to axle portion. The freewheel will generate a greater centrifugal force when it is rotated at a high speed. The inertial effect of the present invention can be enhanced when the rotational speed is increasing progressively, so the curve of inertial weight is elongated obviously. The whole weight of the freewheel is reduced effectively.Type: GrantFiled: April 27, 2012Date of Patent: February 4, 2014Assignee: Tsung-Jen ChenInventors: Tsung-Jen Chen, Chia-Jen Cheng
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Patent number: 8624392Abstract: A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.Type: GrantFiled: June 3, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Chia-Jen Cheng, Hsiu-Mei Yu
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Publication number: 20130283964Abstract: A freewheel structure includes a wheel frame and at least one weight block. The wheel frame has a central axle portion and a flange portion around an outer edge thereof. The axle portion is for insertion of an axle member. The weight block is selectively located between the axle portion and the flange portion, so that the weight block has a certain distance relative to axle portion. The freewheel will generate a greater centrifugal force when it is rotated at a high speed. The inertial effect of the present invention can be enhanced when the rotational speed is increasing progressively, so the curve of inertial weight is elongated obviously. The whole weight of the freewheel is reduced effectively.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Inventors: Tsung-Jen CHEN, Chia-Jen CHENG
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Publication number: 20120306070Abstract: A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.Type: ApplicationFiled: June 3, 2011Publication date: December 6, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Chia-Jen Cheng, Hsiu-Mei Yu
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Patent number: 7863742Abstract: An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line.Type: GrantFiled: November 1, 2007Date of Patent: January 4, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Mei Yu, Tjandra Winata Karta, Daniel Yang, Shih-Ming Chen, Chia-Jen Cheng
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Patent number: 7781140Abstract: A method for removing dry film resist (DFR) from a fine pitch solder bump array on a semiconductor wafer provides for pre-soaking the wafer in a chemical bath then turbulently exposing the wafer to a chemical solution, both steps taking place in batch processing with the wafers processed in a vertical position. The wafers are then individually processed through a chemical spinning operation in which a chemical solution is dispensed from a spray nozzle while motion such as spinning is imparted the horizontally disposed wafer. The spin speed of the chemical spraying process may then be increased to accelerate physical removal of residue. Deionized water rinsing and spin-drying provide a solder bump array void of any DFR or other residuals.Type: GrantFiled: August 17, 2006Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Min Tseng, Hsiu-Mei Yu, Wen-Hsiang Tseng, Chia-Jen Cheng, Yu-Lung Feng, Tung-Wen Hsieh
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Publication number: 20090115058Abstract: An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Inventors: Hsiu-Mei Yu, Tjandra Winata Karta, Daniel Yang, Shih-Ming Chen, Chia-Jen Cheng
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Publication number: 20090026608Abstract: A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Inventors: Mon-Chin Tsai, Hsiu-Mei Yo, Chien-Min Lin, Chia-Jen Cheng, Li-Hsin Tseng
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Publication number: 20080303154Abstract: An integrated circuit structure and methods for forming the same are provided. The method includes providing a substrate; forming a through-silicon via (TSV) opening extending into the substrate; forming an under-bump metallurgy (UBM) in the TSV opening, wherein the UBM extends out of the TSV opening; filling the TSV opening with a metallic material; forming a patterned cap layer on the metallic material; and etching a portion of the UBM outside the TSV opening, wherein the patterned cap layer is used as a mask.Type: ApplicationFiled: June 11, 2007Publication date: December 11, 2008Inventors: Hon-Lin Huang, Boe Su, Li-Hsin Tseng, Chia-Jen Cheng, Hsiu-Mei Yu