Abstract: A controller for managing a battery pack includes: a detection terminal, for transmitting an enable signal when values of battery parameters for the battery pack satisfy a sleep condition, where the enable signal enables the detection circuit to detect whether the battery pack is connected to a load and whether the battery pack is connected to the charger; and a receiving terminal, for receiving a detection result transmitted by the detection circuit. The detection result indicates whether the battery pack is connected to at least one of the load and charger. The controller controls the battery pack to enter a sleep mode of the sleep modes based on the detection result. The controller also includes a control terminal, for transmitting a control signal to control an on/off state of a charging switch and/or a discharging switch. The control signal is generated by the controller based on the detection result.

Abstract: A circuit board detection device includes a base, a stage assembly, a first gantry support, and a first probe assembly. The stage assembly is arranged on the base and includes a linear drive module, a rotary motor, and a platform. The platform is configured to carry a circuit board and can be driven by the linear drive module to move along a first axial direction. The platform can also be driven by the rotary motor to rotate relative to a first rotation axis. The first gantry support is fixed on the base and includes a first beam. The first beam extends along a second axial direction perpendicular to the first axial direction to span over the linear drive module, and includes a first probe guide rail. The first probe assembly is arranged on the first probe guide rail to be movable along the second axial direction.

Abstract: The present application discloses a semiconductor packaging structure and a manufacturing method of the same that could be commonly used for lead frame products and substrate products. The semiconductor packaging structure includes: a base layer (lead frame or organic substrate); a die, disposed on the base layer; a molding compound, filled over the base layer and surrounding the die; a shielding layer, covering the top surface and a side surface of the molding compound; and a bonding wire, having a first terminal and a second terminal, wherein the bonding wire extends the side surface of the molding compound, thus allowing the first terminal of the bonding wire to contact an inner side of the shielding layer.

Abstract: A package method of modular stacked semiconductor package is disclosed. A carrier and a plurality of the chip modules are provided. A plurality of redistribution layers are respectively formed in device areas of the carrier. The chip modules are stacked on the corresponding device areas of the carrier and are electrically connected to each other. A molding compound is formed on the redistribution layers on the carrier to encapsulate the chip modules. The carrier is removed to expose the redistribution layers. A plurality of solder balls are formed on the exposed redistribution layers. The molding compound is cut along adjacent edges of the device areas to form a plurality of modular stacked semiconductor packages. Since the chip modules are previously fabricated, connecting quality among the stacked chip modules is enhanced and is not affected by positioning error.

Abstract: A package method of modular stacked semiconductor package is disclosed. A carrier and a plurality of the chip modules are provided. A plurality of redistribution layers are respectively formed in device areas of the carrier. The chip modules are stacked on the corresponding device areas of the carrier and are electrically connected to each other. A molding compound is formed on the redistribution layers on the carrier to encapsulate the chip modules. The carrier is removed to expose the redistribution layers. A plurality of solder balls are formed on the exposed redistribution layers. The molding compound is cut along adjacent edges of the device areas to form a plurality of modular stacked semiconductor packages. Since the chip modules are previously fabricated, connecting quality among the stacked chip modules is enhanced and is not affected by positioning error.

Abstract: A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.

Abstract: Raw data from chambers is received. Based on received raw data, if a fault exists in operations of the chambers is detected. The detecting includes at least one of operations outlined below. Sigma values respectively corresponding to the chambers are generated based on the raw data of the chambers. A determination is made to determine whether a sigma ratio corresponding to the sigma values is smaller than a threshold value. Mean outlier indexes respectively corresponding to the chambers is generated by executing a mean matching process for the chambers in a condition that the sigma ratio is smaller than the threshold value. One of the chambers, which has a worst first mean outlier index of the first mean outlier indexes, is identified as a target chamber having fault operation.

Abstract: A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.

Abstract: A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

Abstract: A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

Abstract: A heat-dissipating semiconductor package includes a substrate, a chip, a first encapsulation body, a second encapsulation body and a heat sink. The substrate has an inner surface. The chip is disposed on the inner surface of the substrate. The first encapsulation body is formed on the inner surface of the substrate and encapsulates the chip. The second encapsulation body is formed on the first encapsulation body and a periphery area of the inner surface to encapsulate sidewalls and a top surface of the first encapsulation body and cover the periphery area of the inner surface. Wherein, the Young's modulus of the second encapsulation body is less than the Young's modulus of the first encapsulation body. The heat sink is attached to the second encapsulation body. Thereby, the design of the heat-dissipating semiconductor package utilizes multiple encapsulation bodies to reduce the package warpage after installing the heat sink.

Abstract: A heat-dissipating semiconductor package includes a substrate, a chip, a first encapsulation body, a second encapsulation body and a heat sink. The substrate has an inner surface. The chip is disposed on the inner surface of the substrate. The first encapsulation body is formed on the inner surface of the substrate and encapsulates the chip. The second encapsulation body is formed on the first encapsulation body and a periphery area of the inner surface to encapsulate sidewalls and a top surface of the first encapsulation body and cover the periphery area of the inner surface. Wherein, the Young's modulus of the second encapsulation body is less than the Young's modulus of the first encapsulation body. The heat sink is attached to the second encapsulation body. Thereby, the design of the heat-dissipating semiconductor package utilizes multiple encapsulation bodies to reduce the package warpage after installing the heat sink.

Abstract: A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

Abstract: A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

Abstract: Raw data from chambers is received. Based on received raw data, if a fault exists in operations of the chambers is detected. The detecting includes at least one of operations outlined below. Sigma values respectively corresponding to the chambers are generated based on the raw data of the chambers. A determination is made to determine whether a sigma ratio corresponding to the sigma values is smaller than a threshold value. Mean outlier indexes respectively corresponding to the chambers is generated by executing a mean matching process for the chambers in a condition that the sigma ratio is smaller than the threshold value. One of the chambers, which has a worst first mean outlier index of the first mean outlier indexes, is identified as a target chamber having fault operation.