Abstract: Disclosed are a conductive film and a test component. A conductive film includes a supporting layer, a circuit layer and a protective layer. The supporting layer has a first surface and a second surface opposite to the first surface. The supporting layer supports the circuit layer. The circuit layer includes a first protruding part, a second protruding part and a connecting part. The first protruding part is disposed on the first surface. The second protruding part is disposed on the second surface. The connecting part is disposed between the first protruding part and the second protruding part. The first protruding part is connected to the second protruding part through the connecting part. The protective layer covers the first protruding part. The conductive film and the test component of the disclosed embodiments may have a buffering effect or increase the service life.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A testing device includes a circuit board, a carrier, a probe pin, a main body, a shaft, a pressing portion and a resilient spiral spring. The carrier is used to hold a device under test (DUT). The probe pin is electrically connected to the circuit board and the DUT. The shaft is movably connected to the main body with a screwing rotation method. The pressing portion is connected to one end surface of the shaft. The resilient spiral spring is retractably coiled on the shaft, and one end of the resilient spiral spring being far away from the shaft extends in a transverse direction intersecting an axial direction of the shaft.

Abstract: A wafer shipping device includes a box body having a first slot, a cover body having a second slot, and a sensing circuit module having a first sensor, a second sensor, an indication circuit and a warning device. The first slot and the second slot are used to collaboratively hold a semiconductor wafer. The first sensor and the first sensor are located in the box body for independently sensing whether the semiconductor wafer is inserted in the first slot and the second slot respectively. The indication circuit is electrically connected to the first sensor, the second sensor and the warning device, and correspondingly issued one of types of indication signals to the warning device in response to sensing results obtained from the first sensor and the second sensor respectively.

Abstract: A cleaning apparatus includes a case and a cleaning head. The cleaning head is disposed on the case, and provided with a plurality of tines. The tines are separately arranged abreast. The tines are used to extend into gaps between plural conductive terminals of a semiconductor product for cleaning the semiconductor product.

Abstract: A testing device includes a circuit board, a carrier, a probe pin, a main body, a shaft, a pressing portion and a resilient spiral spring. The carrier is used to hold a device under test (DUT). The probe pin is electrically connected to the circuit board and the DUT. The shaft is movably connected to the main body with a screwing rotation method. The pressing portion is connected to one end surface of the shaft. The resilient spiral spring is retractably coiled on the shaft, and one end of the resilient spiral spring being far away from the shaft extends in a transverse direction intersecting an axial direction of the shaft.

Abstract: A cleaning apparatus includes a case and a cleaning head. The cleaning head is disposed on the case, and provided with a plurality of tines. The tines are separately arranged abreast. The tines are used to extend into gaps between plural conductive terminals of a semiconductor product for cleaning the semiconductor product.

Abstract: Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.

Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

Abstract: Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.

Abstract: A method of manufacturing an integrated circuit package includes providing a ball grid array (BGA) module including BGA balls on a side of the BGA module; providing a base substrate; and placing the BGA module on the base substrate. The BGA balls are placed between the BGA module and the base substrate. An adhesive is applied between and contacting the BGA module and the base substrate. The adhesive is then cured. The BGA balls are re-flowed after the step of curing the adhesive.

Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

Abstract: A method of manufacturing an integrated circuit package includes providing a ball grid array (BGA) module including BGA balls on a side of the BGA module; providing a base substrate; and placing the BGA module on the base substrate. The BGA balls are placed between the BGA module and the base substrate. An adhesive is applied between and contacting the BGA module and the base substrate. The adhesive is then cured. The BGA balls are re-flowed after the step of curing the adhesive.

Abstract: A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.

Abstract: The present invention utilizes wafer acceptance testing equipment to fast monitor the quality of an insulation layer. A plurality of swing time-dependent DC ramping voltages are applied to one of the electrode plates in a capacitor and each corresponding leakage current is measured to calculate each corresponding ? value. Then, a ratio of each ? value is calculated and a ?-voltage curve is plotted to actually simulate the device failure.

Abstract: The present invention utilizes to wafer acceptance testing equipment to fast monitor the quality of a tunnel oxide layer. First, a control gate and a floating gate in a memory cell are electrically connected. Then a plurality of swing time-dependent DC ramping voltages are applied and each corresponding gate leakage current is measured to calculate each corresponding ? value. Finally a ratio of each ? value is calculated and a ?-gate voltage curve is plotted to actually simulate the device failure.

Abstract: The present invention utilizes wafer acceptance testing equipment to fast monitor the quality of an insulation layer. A plurality of swing time-dependent DC ramping voltages are applied to one of the electrode plates in a capacitor and each corresponding leakage current is measured to calculate each corresponding ? value. Then, a ratio of each ? value is calculated and a ?? voltage curve is plotted to actually simulate the device failure.

Abstract: The present invention utilizes a wafer acceptance testing equipment to fast monitor the quality of a tunnel oxide layer. First, a control gate and a floating gate in a memory cell are electrically connected. Then a plurality of swing time-dependent DC ramping voltages are applied and each corresponding gate leakage current is measured to calculate each corresponding &bgr; value. Finally a ratio of each &bgr; value is calculated and a &bgr;-gate voltage curve is plotted to actually simulate the device failure.