Patents by Inventor Chia-Jen Yu

Chia-Jen Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7986931
    Abstract: An echo cancellation circuit for an RFID reader and the method thereof are provided. The echo cancellation circuit includes a gain calculator, a gain adjustment circuit, and a subtraction circuit. The gain calculator provides a complex gain value according to a carrier signal and a received signal through an adaptive algorithm. The gain adjustment circuit is coupled to the gain calculator. The gain adjustment circuit multiplies the carrier signal by the complex gain value, and outputs the result of the multiplication. The subtraction circuit is coupled to the gain adjustment circuit. The subtraction circuit subtracts the output of the gain adjustment circuit from the received signal, and then provides the result of the subtraction as the output signal of the echo cancellation circuit.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: July 26, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Hung Lin, Chin-Fu Li, Chia-Jen Yu, Jiunn-Tsair Chen
  • Patent number: 7742547
    Abstract: A method and a system for reading radio frequency identification (RFID) tags are provided. The method includes the following steps. First, receive a tag signal from the RFID tag. Recover a data clock rate from the tag signal according to statistics of pulse lengths of the tag signal. Next, determine a frame synchronization point of a data frame following a preamble in the tag signal by a signal correlation between the preamble and a predetermined signal pattern according to the data clock rate. Finally, decode the data frame by using an adaptive Viterbi algorithm on an extended trellis diagram. The extended trellis diagram includes a plurality of nodes and a plurality of branches connecting the nodes. The nodes and the branches are arranged according to the modulation scheme of the data frame and possible variations of the data clock rate.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: June 22, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Hung Lin, Chia-Jen Yu, Jiunn-Tsair Chen
  • Publication number: 20080136645
    Abstract: An echo cancellation circuit for an RFID reader and the method thereof are provided. The echo cancellation circuit includes a gain calculator, a gain adjustment circuit, and a subtraction circuit. The gain calculator provides a complex gain value according to a carrier signal and a received signal through an adaptive algorithm. The gain adjustment circuit is coupled to the gain calculator. The gain adjustment circuit multiplies the carrier signal by the complex gain value, and outputs the result of the multiplication. The subtraction circuit is coupled to the gain adjustment circuit. The subtraction circuit subtracts the output of the gain adjustment circuit from the received signal, and then provides the result of the subtraction as the output signal of the echo cancellation circuit.
    Type: Application
    Filed: April 17, 2007
    Publication date: June 12, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Hung Lin, Chin-Fu Li, Chia-Jen Yu, Jiunn-Tsair Chen
  • Publication number: 20080129505
    Abstract: A method and a system for reading radio frequency identification (RFID) tags are provided. The method includes the following steps. First, receive a tag signal from the RFID tag. Recover a data clock rate from the tag signal according to statistics of pulse lengths of the tag signal. Next, determine a frame synchronization point of a data frame following a preamble in the tag signal by a signal correlation between the preamble and a predetermined signal pattern according to the data clock rate. Finally, decode the data frame by using an adaptive Viterbi algorithm on an extended trellis diagram. The extended trellis diagram includes a plurality of nodes and a plurality of branches connecting the nodes. The nodes and the branches are arranged according to the modulation scheme of the data frame and possible variations of the data clock rate.
    Type: Application
    Filed: May 23, 2007
    Publication date: June 5, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Hung Lin, Chia-Jen Yu, Jiunn-Tsair Chen