Patents by Inventor Chia-Jui Yang

Chia-Jui Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11911951
    Abstract: A matte film for hot pressing and a manufacturing method thereof are provided. The manufacturing method includes steps of forming at least one polyester composition into an unstretched polyester thick film and stretching the unstretched polyester thick film in a machine direction (MD) and a transverse direction (TD). The polyester composition includes 81% to 97.9497% by weight of a polyester resin, 0.02% to 2% by weight of an antioxidative ingredient, 0.0003% to 1% by weight of a nucleating agent, 0.01% to 2% by weight of a flow aid, 0.01% to 2% by weight of a polyester modifier, 0.01% to 2% by weight of an inorganic filler, and 2% to 10% by weight of silica particles. The polyester resin has an intrinsic viscosity between 0.60 dl/g and 0.80 dl/g.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 27, 2024
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wen-Cheng Yang, Wen-Jui Cheng, Chia-Yen Hsiao, Chien-Chih Lin
  • Patent number: 11570103
    Abstract: A network communication device includes a plurality of ports, a memory, and a processor. The plurality of ports is configured to receive a packet. A memory is configured to store a first lookup table and a second lookup table. An entry of the first lookup table includes a flag field. An entry of the second lookup table includes an entry address of the first lookup table. The processor is coupled to the memory and the plurality of ports. The network communication device is configured to: analyze the packet by a software or hardware to obtain a source Media Access Control (MAC) address; obtain, according to the source MAC address of the packet, the entry of the first lookup table; read the flag field of the entry; and determine, according to the flag field, whether the entry is referred by the second lookup table.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: January 31, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jeong-Fa Sheu, Chia-Jui Yang, Jun-An Ding
  • Publication number: 20210266258
    Abstract: A network communication device includes a plurality of ports, a memory, and a processor. The plurality of ports is configured to receive a packet. A memory is configured to store a first lookup table and a second lookup table. An entry of the first lookup table includes a flag field. An entry of the second lookup table includes an entry address of the first lookup table. The processor is coupled to the memory and the plurality of ports. The network communication device is configured to: analyze the packet by a software or hardware to obtain a source Media Access Control (MAC) address; obtain, according to the source MAC address of the packet, the entry of the first lookup table; read the flag field of the entry; and determine, according to the flag field, whether the entry is referred by the second lookup table.
    Type: Application
    Filed: September 18, 2020
    Publication date: August 26, 2021
    Inventors: Jeong-Fa SHEU, Chia-Jui YANG, Jun-An DING
  • Patent number: 11073555
    Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 27, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Yen Chen, Jeong-Fa Sheu, Chia-Jui Yang, Po-Lin Chen
  • Patent number: 11061073
    Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 13, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Yen Chen, Jeong-Fa Sheu, Chia-Jui Yang, Po-Lin Chen
  • Publication number: 20200217887
    Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.
    Type: Application
    Filed: December 3, 2019
    Publication date: July 9, 2020
    Inventors: Ying-Yen CHEN, Jeong-Fa SHEU, Chia-Jui YANG, Po-Lin CHEN
  • Publication number: 20200217886
    Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.
    Type: Application
    Filed: December 3, 2019
    Publication date: July 9, 2020
    Inventors: Ying-Yen Chen, Jeong-Fa Sheu, Chia-Jui Yang, Po-Lin Chen