Patents by Inventor Chia Jung Chang

Chia Jung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240024206
    Abstract: A separating membrane for dental surgeries and a method for manufacturing the same are provided. The separating membrane has biodegradability, and includes a biodegradable porous base layer and a hydrophilic substance. The hydrophilic substance is bonded to the biodegradable porous base layer, and is selected from the group consisting of hyaluronic acid, derivatives of the hyaluronic acid, and water-soluble vitamins. An outer surface of the separating membrane has a water contact angle of less than 80°.
    Type: Application
    Filed: November 28, 2022
    Publication date: January 25, 2024
    Inventors: TE-CHAO LIAO, Min-Fan Chung, CHIA-JUNG CHANG, CHING-YAO YUAN
  • Publication number: 20240026266
    Abstract: A cell culture bag is provided. The cell culture bag includes a plastic bag body and a hydration layer. A culture space is formed in the plastic bag body. The plastic bag body has a zwitterionic polymer plastic surface facing the culture space. A material forming the zwitterionic polymer plastic surface includes a zwitterionic polymer. The hydration layer is attached onto the zwitterionic polymer plastic surface, and the culture space is surrounded by the hydration layer.
    Type: Application
    Filed: December 8, 2022
    Publication date: January 25, 2024
    Inventors: TE-CHAO LIAO, Min-Fan Chung, CHING-YAO YUAN, CHIA-JUNG CHANG
  • Patent number: 11863189
    Abstract: An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Kai Tsai, Chia-Hui Chen, Chia-Jung Chang
  • Publication number: 20230344428
    Abstract: A method of operating a power-on (PO) signal generator (which generates a PO signal and includes a supply-variation sensitivity-reducing (SVSR) load coupled between a first reference voltage and a first node, and a first transistor coupled between the first node and a second reference voltage, the SVSR load including a first resistor coupled between the first reference voltage and a second node, and a second transistor coupled between the second node and the first node, each of a control input of the SVSR load and a gate terminal the first transistor being coupled to a monitored voltage) includes: when the monitored voltage rises above a threshold voltage of the first transistor, turning on the first transistor, and pulling first and second voltages correspondingly on the first and second nodes, a third voltage of the second transistor, and the PO signal down to a logical low value.
    Type: Application
    Filed: July 4, 2023
    Publication date: October 26, 2023
    Inventors: Shao-Te WU, Chia-Jung CHANG, Shih-Peng CHANG
  • Patent number: 11790932
    Abstract: A system may include a first acoustic event detection (AED) component configured to detect a predetermined set of acoustic events, and include a second AED component configured to detect custom acoustic events that a user configures a device to detect. The first and second AED components are configured to perform task-specific processing, and may receive as input the same acoustic feature data corresponding to audio data that potentially represents occurrence of one or more events. Based on processing by the first and second AED components, a device may output data indicating that one or more acoustic events occurred, where the acoustic events may be a predetermined acoustic event and/or a custom acoustic event.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 17, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Qingming Tang, Chieh-Chi Kao, Qin Zhang, Ming Sun, Chao Wang, Sumit Garg, Rong Chen, James Garnet Droppo, Chia-Jung Chang
  • Publication number: 20230327429
    Abstract: Disclosed herein are related to a device for electrostatic discharge (ESD) protection. In one aspect, a device includes an ESD detector to detect an ESD at a pad. In one aspect, the device includes P-type transistors and N-type transistors connected in series with each other. In one aspect, the drive circuit is configured to provide an output signal to the pad. In one aspect, the device includes a first protection circuit operating in a power domain. In one aspect, in response to the ESD detected by the ESD detector, the first protection circuit is configured to disable the P-type transistors. In one aspect, the device includes a second protection circuit operating in another power domain. In one aspect, in response to the ESD detected by the ESD detector, the second protection circuit is configured to disable the N-type transistors.
    Type: Application
    Filed: July 15, 2022
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hui Chen, Chia-Jung Chang
  • Patent number: 11783765
    Abstract: A light emitting diode (LED) driver circuit is configured to drive plural LEDs which are respectively coupled to m scan-lines and n data-lines, wherein m and n are both integers greater than or equal to one. During a driving stage, each of the LEDs is controlled to emit light according to the electrical characteristics on the corresponding scan-line and on the corresponding data-line where the LED is coupled to. The LED driver circuit includes: a power saving control circuit which includes a storage capacitor; a pre-discharging circuit configured to pre-discharge the charges on the m scan-lines to the storage capacitor during a pre-discharging stage; and a pre-charging circuit configured to pre-charge the n data-lines by the charges stored in the storage capacitor during a pre-charging stage.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: October 10, 2023
    Inventors: Chia-Jung Chang, Shao-Ming Chang, Hsiang-Feng Yu, Tso-Yu Wu, Yu-Pin Tseng
  • Publication number: 20230299770
    Abstract: A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Chia-Hui Chen, Chia-Jung Chang
  • Publication number: 20230299576
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.
    Type: Application
    Filed: May 24, 2023
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Yu-Ti SU, Chia-Wei HSU, Ming-Fu TSAI, Shu-Yu SU, Li-Wei CHU, Jam-Wem LEE, Chia-Jung CHANG, Hsiang-Hui CHENG
  • Publication number: 20230266384
    Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Inventors: Hsiang-Hui CHENG, Chia-Jung CHANG
  • Patent number: 11714215
    Abstract: An optical lens, mold for optical lens and manufacturing method thereof are provided, wherein the optical lens includes a spiral surface spiraling around an axial direction and an intermediate structure around which the spiral surface spirals, the intermediate structure extends axially relative to a side of the spiral surface, and two ends of the spiral surface defines a stepped difference. The structure of the mold and the optical lens are correspondingly complementary. The manufacturing method of the mold includes following steps of: providing a base, the base including a processing surface; processing the processing surface to form the spiral surface, the intermediate structure and the stepped difference of the mold.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 1, 2023
    Assignee: ORANGETEK CORPORATION
    Inventors: Chun-Chieh Chen, Chia-Jung Chang, Chih-Yi Huang, Chun-Yi Yeh
  • Patent number: 11710962
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.
    Type: Grant
    Filed: May 29, 2022
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Publication number: 20230215861
    Abstract: An electro-static discharge (ESD) protection network for an input/output (I/O) pad includes a driver stack including an upper branch and a lower branch, the upper branch being electrically connected between a first node that has a first reference voltage and the I/O pad, and the lower branch being electrically connected between the I/O pad and a second node that has a second reference voltage; a first ESD device electrically connected between the I/O pad and a third node that has a third reference voltage; and a power clamp between the third node and the second node.
    Type: Application
    Filed: May 2, 2022
    Publication date: July 6, 2023
    Inventors: Chia-Hui CHEN, Chia-Jung CHANG, Bo-Ting CHEN
  • Patent number: 11695414
    Abstract: A method of generating multiple gating signals for a multi-gated input/output (I/O) system. The system includes an output level shifter and an output driver which are coupled in series between an output node of a core circuit and an external terminal of a corresponding system. The method includes: generating first and second gating signals having corresponding first and second waveforms, the first waveform transitioning from a non-enabling state to an enabling state before the second waveform transitions from the non-enabling state to the enabling state; receiving the first gating signal at the output level shifter; and receiving the second gating signal at the output driver.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Te Wu, Chia-Jung Chang, Shih-Peng Chang
  • Patent number: 11695416
    Abstract: A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: July 4, 2023
    Inventors: Wan-Yen Lin, Chia-Hui Chen, Chia-Jung Chang
  • Publication number: 20230186939
    Abstract: A system may include a first acoustic event detection (AED) component configured to detect a predetermined set of acoustic events, and include a second AED component configured to detect custom acoustic events that a user configures a device to detect. The first and second AED components are configured to perform task-specific processing, and may receive as input the same acoustic feature data corresponding to audio data that potentially represents occurrence of one or more events. Based on processing by the first and second AED components, a device may output data indicating that one or more acoustic events occurred, where the acoustic events may be a predetermined acoustic event and/or a custom acoustic event.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Inventors: Qingming Tang, Chieh-Chi Kao, Qin Zhang, Ming Sun, Chao Wang, Sumit Garg, Rong Chen, James Garnet Droppo, Chia-Jung Chang
  • Publication number: 20230152219
    Abstract: An optical water-quality detection apparatus includes a detection device, a biofilm-inhibition light source, a detection light source and a sensor. The detection device includes a detection chamber. The biofilm-inhibition light source is disposed outside the detection chamber and configured to emit biofilm-inhibition light. The detection light source is disposed outside the detection chamber and configured to emit detection light. The sensor is configured to sense the detection light penetrating the detection chamber. A beam of the detection light and a beam of the inhibition light overlaps as penetrating the detection chamber.
    Type: Application
    Filed: August 10, 2022
    Publication date: May 18, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Jung CHANG, Jui-Hung TSAI, Ying-Hao WANG, Chih-Hao HSU
  • Patent number: 11639958
    Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and the pad voltage terminal. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The fourth transistor is in a second well different from the first well, and is separated from the first well in a first direction.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Hui Cheng, Chia-Jung Chang
  • Publication number: 20230127483
    Abstract: An optical transmission device is provided. A substrate includes an optical transmission channel exposed on its end surface, and a first positioning portion. A jumper includes a mounting portion abutting the end surface and a second positioning portion engaged to the first positioning portion. An optical fiber is mounted to the mounting portion, and the end surface of the optical fiber aligns with the optical transmission channel. The coupling method of the optical transmission device includes steps: forming at least one first hole on the substrate, forming an optical transmission layer with at least one optical transmission channel on the substrate, forming an alignment mark on the optical transmission layer within the first hole, forming at least one second hole on the substrate based on the alignment mark, and connecting the jumper to the second hole and make the jumper abutting against the substrate.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 27, 2023
    Inventors: CHUN-CHIEH CHEN, PO-TING CHEN, CHAO-HUI KUO, CHIA-JUNG CHANG
  • Publication number: 20220365130
    Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and the pad voltage terminal. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The fourth transistor is in a second well different from the first well, and is separated from the first well in a first direction.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Hsiang-Hui CHENG, Chia-Jung CHANG