Abstract: A blood container and a method for manufacturing the same are provided. The blood container includes a container body and an anti-fouling layer to be hydrated. The container body has an inner wall surface, and the anti-fouling layer to be hydrated covers the inner wall surface and contains a hydration polymer. A covering rate of the hydration polymer on the inner wall surface is from 50% to 100%.

Abstract: A switching regulator includes: a power stage circuit, a control circuit and an operation clock signal generator circuit. The operation clock signal generator circuit includes: a time point option unit generating a time point option signal according to a phase node voltage during a ringing period subsequent to a blanking period, to indicate at least one available turn-on time point, or generating a lowest voltage time point signal according to the phase node voltage during a tolerance period, to indicate a lowest voltage time point; and a time point deciding unit deciding the tolerance period according to a base clock signal and a tolerable frequency range and select the available turn-on time point or the lowest voltage time point within the tolerance period as a decided time point, to generate the operation clock signal.

Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.

Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.

Abstract: An acoustic event detection system may employ one or more recurrent neural networks (RNNs) to extract features from audio data, and use the extracted features to determine the presence of an acoustic event. The system may use self-attention to emphasize features extracted from portions of audio data that may include features more useful for detecting acoustic events. The system may perform self-attention in an iterative manner to reduce the amount of memory used to store hidden states of the RNN while processing successive portions of the audio data. The system may process the portions of the audio data using the RNN to generate a hidden state for each portion. The system may calculate an interim embedding for each hidden state. An interim embedding calculated for the last hidden state may be normalized to determine a final embedding representing features extracted from the input data by the RNN.

Abstract: An integrated circuit includes an upper threshold circuit configured to set a logic level of a first enabling signal, a lower threshold circuit configured to set a logic level of a second enabling signal, and a control circuit configured to change an output voltage signal in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively. In the control circuit, a first switch is electrically connected to a second switch at a buffer output node. The control circuit includes a regenerative circuit configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.

Abstract: A system may include a first acoustic event detection (AED) component configured to detect a predetermined set of acoustic events, and include a second AED component configured to detect custom acoustic events that a user configures a device to detect. The first and second AED components are configured to perform task-specific processing, and may receive as input the same acoustic feature data corresponding to audio data that potentially represents occurrence of one or more events. Based on processing by the first and second AED components, a device may output data indicating that one or more acoustic events occurred, where the acoustic events may be a predetermined acoustic event and/or a custom acoustic event.

Abstract: An optical water-quality detection apparatus includes a detection device, a biofilm-inhibition light source, a detection light source and a sensor. The detection device includes a detection chamber. The biofilm-inhibition light source is disposed outside the detection chamber and configured to emit biofilm-inhibition light. The detection light source is disposed outside the detection chamber and configured to emit detection light. The sensor is configured to sense the detection light penetrating the detection chamber. A beam of the detection light and a beam of the inhibition light overlaps as penetrating the detection chamber.

Abstract: A cell culture bag is provided. The cell culture bag includes a plastic bag body and a hydration layer. A culture space is formed in the plastic bag body. The plastic bag body has a zwitterionic polymer plastic surface facing the culture space. A material forming the zwitterionic polymer plastic surface includes a zwitterionic polymer. The hydration layer is attached onto the zwitterionic polymer plastic surface, and the culture space is surrounded by the hydration layer.

Abstract: A separating membrane for dental surgeries and a method for manufacturing the same are provided. The separating membrane has biodegradability, and includes a biodegradable porous base layer and a hydrophilic substance. The hydrophilic substance is bonded to the biodegradable porous base layer, and is selected from the group consisting of hyaluronic acid, derivatives of the hyaluronic acid, and water-soluble vitamins. An outer surface of the separating membrane has a water contact angle of less than 80°.

Abstract: An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.

Abstract: A method of operating a power-on (PO) signal generator (which generates a PO signal and includes a supply-variation sensitivity-reducing (SVSR) load coupled between a first reference voltage and a first node, and a first transistor coupled between the first node and a second reference voltage, the SVSR load including a first resistor coupled between the first reference voltage and a second node, and a second transistor coupled between the second node and the first node, each of a control input of the SVSR load and a gate terminal the first transistor being coupled to a monitored voltage) includes: when the monitored voltage rises above a threshold voltage of the first transistor, turning on the first transistor, and pulling first and second voltages correspondingly on the first and second nodes, a third voltage of the second transistor, and the PO signal down to a logical low value.

Abstract: A system may include a first acoustic event detection (AED) component configured to detect a predetermined set of acoustic events, and include a second AED component configured to detect custom acoustic events that a user configures a device to detect. The first and second AED components are configured to perform task-specific processing, and may receive as input the same acoustic feature data corresponding to audio data that potentially represents occurrence of one or more events. Based on processing by the first and second AED components, a device may output data indicating that one or more acoustic events occurred, where the acoustic events may be a predetermined acoustic event and/or a custom acoustic event.

Abstract: Disclosed herein are related to a device for electrostatic discharge (ESD) protection. In one aspect, a device includes an ESD detector to detect an ESD at a pad. In one aspect, the device includes P-type transistors and N-type transistors connected in series with each other. In one aspect, the drive circuit is configured to provide an output signal to the pad. In one aspect, the device includes a first protection circuit operating in a power domain. In one aspect, in response to the ESD detected by the ESD detector, the first protection circuit is configured to disable the P-type transistors. In one aspect, the device includes a second protection circuit operating in another power domain. In one aspect, in response to the ESD detected by the ESD detector, the second protection circuit is configured to disable the N-type transistors.

Abstract: A light emitting diode (LED) driver circuit is configured to drive plural LEDs which are respectively coupled to m scan-lines and n data-lines, wherein m and n are both integers greater than or equal to one. During a driving stage, each of the LEDs is controlled to emit light according to the electrical characteristics on the corresponding scan-line and on the corresponding data-line where the LED is coupled to. The LED driver circuit includes: a power saving control circuit which includes a storage capacitor; a pre-discharging circuit configured to pre-discharge the charges on the m scan-lines to the storage capacitor during a pre-discharging stage; and a pre-charging circuit configured to pre-charge the n data-lines by the charges stored in the storage capacitor during a pre-charging stage.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

Abstract: A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.

Abstract: An optical lens, mold for optical lens and manufacturing method thereof are provided, wherein the optical lens includes a spiral surface spiraling around an axial direction and an intermediate structure around which the spiral surface spirals, the intermediate structure extends axially relative to a side of the spiral surface, and two ends of the spiral surface defines a stepped difference. The structure of the mold and the optical lens are correspondingly complementary. The manufacturing method of the mold includes following steps of: providing a base, the base including a processing surface; processing the processing surface to form the spiral surface, the intermediate structure and the stepped difference of the mold.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.