Patents by Inventor Chia-Jung Chiu

Chia-Jung Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250145040
    Abstract: A method for monitoring an electric vehicle charging apparatus is provided. A charging pile that includes a power meter and a processor is used to provide a charging current to an electric vehicle through a charging connector. The power meter detects the charging current to generate an initial current value and an initial power value that correspond to an initial charging time, and a present current value and a present power value that correspond to a present time, so that the processor calculates an initial resistance value and a present resistance value of the charging connector accordingly, and then calculates an estimated present temperature value of the charging connector based on the initial resistance value and the present resistance value. The estimated present temperature value is compared with an over-temperature threshold to determine whether to reduce the charging current.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Inventors: Hsien-Ju WU, Chun-Chieh CHIU, Tai-Chang CHEN, Jinn-Feng JIANG, Chia-Lung HUANG, Mei-Jung CHEN
  • Publication number: 20250125237
    Abstract: Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Inventors: Chih-Hsien Chiu, Ko-Wei Chang, Wen-Jung Tsai, Che-Wei Yu, Chia-Yang Chen
  • Patent number: 12272693
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 8, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chia-Jung Hsu, Chin-Hung Chen
  • Patent number: 12261086
    Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chun-Ya Chiu, Chia-Jung Hsu, Chin-Hung Chen
  • Patent number: 12255093
    Abstract: The present disclosure provides a 3D memory structure such as 3D Flash memory structure applying for 3D AND flash memory and a method of forming the same. An etching stop layer is formed on a substrate including active elements. A stacked layer is formed on the etching stop layer. The stacked layer includes insulation layers and sacrificed layers stacked alternatively on the etching stop layer. A patterning process is performed on the stacked layer to form a first stacked structure above the active elements, a second stacked structure surrounding the first stacked structure, and a trench pattern separating the first stacked structure and the second stacked structure and exposing the etching stop layer. The trench pattern includes asymmetric inner sidewalls and outer sidewalls. The inner sidewalls define sidewalls of the first stacked structure. The outer sidewalls define sidewalls of the second stacked structure that face the first stacked structure.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: March 18, 2025
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Kuan-Yuan Shen, Chung-Hao Fu, Chia-Jung Chiu
  • Patent number: 12245428
    Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: March 4, 2025
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hang-Ting Lue, Chia-Jung Chiu, Teng-Hao Yeh, Guan-Ru Lee
  • Publication number: 20250038061
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic component and a heat dissipation structure having an opening are arranged on a carrier structure, a heat sink is arranged in the opening and bonded to the electronic component, and the electronic component, the heat dissipation structure and the heat sink are covered with an encapsulation layer, such that the heat sink can be arranged according to a heat source of a specific part of the electronic component so as to effectively dissipate heat.
    Type: Application
    Filed: January 12, 2024
    Publication date: January 30, 2025
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chia-Yang CHEN, Chien-Ming CHANG, Po-Hsin TSAI
  • Patent number: 12211776
    Abstract: Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: January 28, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Ko-Wei Chang, Wen-Jung Tsai, Che-Wei Yu, Chia-Yang Chen
  • Publication number: 20240373630
    Abstract: A semiconductor device includes a staircase structure and an extension part. The stacked structure is located on a dielectric substrate. The staircase structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The extension part is located at an end of the lower stair part of the staircase structure. The resistance value of the extension part is different from the resistance value of the plurality of conductive layers.
    Type: Application
    Filed: May 4, 2023
    Publication date: November 7, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Kuan-Yuan Shen, Guan-Ru Lee, Chia-Jung Chiu
  • Publication number: 20240268112
    Abstract: Provided are a semiconductor structure for a 3D memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a substrate having a memory array region and a staircase region, an insulating layer, a stacked structure and a vertical channel (VC) structure. The insulating layer is disposed on the substrate. The stacked structure is disposed on the insulating layer. The stacked structure includes first dielectric layers separated from each other, and the stacked structure in the staircase region has a staircase profile. The VC structure is disposed in the stacked structure in the memory array region and penetrates through the stacked structure. There is a vertical hole in the stacked structure and the insulating layer in the staircase region, and a third dielectric layer is filled in the vertical hole.
    Type: Application
    Filed: February 6, 2023
    Publication date: August 8, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Kuan-Yuan Shen, Chia-Jung Chiu
  • Publication number: 20230371252
    Abstract: A three-dimension memory device, a memory circuit and a production method are provided. The three-dimension memory circuit includes a peripheral circuit, a metal layer, a buffer layer, a poly silicon layer, and a via array. The peripheral circuit is disposed on a substrate. The metal layer covers on the peripheral circuit and is electrically coupled to the peripheral circuit. The buffer layer is disposed on the metal layer. The poly silicon layer receives a reference ground voltage and is disposed on the buffer layer. The via array is disposed in the buffer layer and is used to electrically connect the metal layer and the poly silicon layer.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Kuan-Yuan Shen, Teng-Hao Yeh, Chia-Jung Chiu
  • Publication number: 20230369100
    Abstract: The present disclosure provides a 3D memory structure such as 3D Flash memory structure applying for 3D AND flash memory and a method of forming the same. An etching stop layer is formed on a substrate including active elements. A stacked layer is formed on the etching stop layer. The stacked layer includes insulation layers and sacrificed layers stacked alternatively on the etching stop layer. A patterning process is performed on the stacked layer to form a first stacked structure above the active elements, a second stacked structure surrounding the first stacked structure, and a trench pattern separating the first stacked structure and the second stacked structure and exposing the etching stop layer. The trench pattern includes asymmetric inner sidewalls and outer sidewalls. The inner sidewalls define sidewalls of the first stacked structure. The outer sidewalls define sidewalls of the second stacked structure that face the first stacked structure.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Kuan-Yuan Shen, Chung-Hao Fu, Chia-Jung Chiu
  • Publication number: 20230225126
    Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 13, 2023
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Hang-Ting Lue, Chia-Jung Chiu, Teng-Hao Yeh, Guan-Ru Lee
  • Patent number: 11638379
    Abstract: A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: April 25, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Min-Feng Hung, Chia-Jung Chiu, Guan-Ru Lee
  • Publication number: 20230106571
    Abstract: An embodiment of the present disclosure provides a memory device. The memory device comprises a substrate. A plurality of word line layers are disposed over the substrate. An array of vertical NOR columns is in a first area of the plurality of word line layers. Each vertical NOR column in the array of vertical NOR columns includes a first conductive pillar and a second conductive pillar. Each vertical NOR column comprises a first plurality of memory cells arranged in a NOR configuration formed at cross points of word line layers in the plurality of word line layers with the first and second conductive pillars. An array of vertical NAND columns is in a second area of the plurality of word line layers. Each vertical NAND column in the array of vertical NAND columns includes a memory pillar. Each vertical NAND column comprises a second plurality of memory cells arranged in a NAND configuration formed at cross points of word line layers in the plurality of word line layers with the memory pillar.
    Type: Application
    Filed: January 18, 2022
    Publication date: April 6, 2023
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuan-Yuan SHEN, Chia-Jung CHIU
  • Publication number: 20230088149
    Abstract: Provided is a method of forming a three-dimensional (3D) memory device including: forming a discharging layer and a stack structure on a buffer layer; forming vertical channel structures in the stack structure; forming an opening in the stack structure, wherein the opening includes two first trenches extending along a X direction and two second trenches extending along a Y direction, and the two first trenches and the two second trenches are separated from each other; forming an insulating layer on a sidewall of the opening; removing the discharging layer exposed by the insulating layer to form a cavity connecting the two first trenches and the two second trenches, thereby forming a ring-shaped opening; performing a gate replacement process to replace sacrificial layers of the stack structure by conductive layers; and filling an isolating material in the ring-shaped opening to form an isolating ring structure.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Kuan-Yuan Shen, Chia-Jung Chiu
  • Publication number: 20220052072
    Abstract: A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Min-Feng HUNG, Chia-Jung CHIU, Guan-Ru LEE
  • Patent number: 11195847
    Abstract: A memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 7, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Min-Feng Hung, Chia-Jung Chiu, Guan-Ru Lee
  • Publication number: 20200365611
    Abstract: A memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 19, 2020
    Inventors: Min-Feng HUNG, Chia-Jung CHIU, Guan-Ru LEE
  • Patent number: 9123579
    Abstract: A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: September 1, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Chia-Jung Chiu, Chieh Lo