Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic component and a heat dissipation structure having an opening are arranged on a carrier structure, a heat sink is arranged in the opening and bonded to the electronic component, and the electronic component, the heat dissipation structure and the heat sink are covered with an encapsulation layer, such that the heat sink can be arranged according to a heat source of a specific part of the electronic component so as to effectively dissipate heat.

Abstract: Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.

Abstract: A semiconductor device includes a staircase structure and an extension part. The stacked structure is located on a dielectric substrate. The staircase structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The extension part is located at an end of the lower stair part of the staircase structure. The resistance value of the extension part is different from the resistance value of the plurality of conductive layers.

Abstract: Provided are a semiconductor structure for a 3D memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a substrate having a memory array region and a staircase region, an insulating layer, a stacked structure and a vertical channel (VC) structure. The insulating layer is disposed on the substrate. The stacked structure is disposed on the insulating layer. The stacked structure includes first dielectric layers separated from each other, and the stacked structure in the staircase region has a staircase profile. The VC structure is disposed in the stacked structure in the memory array region and penetrates through the stacked structure. There is a vertical hole in the stacked structure and the insulating layer in the staircase region, and a third dielectric layer is filled in the vertical hole.

Abstract: A three-dimension memory device, a memory circuit and a production method are provided. The three-dimension memory circuit includes a peripheral circuit, a metal layer, a buffer layer, a poly silicon layer, and a via array. The peripheral circuit is disposed on a substrate. The metal layer covers on the peripheral circuit and is electrically coupled to the peripheral circuit. The buffer layer is disposed on the metal layer. The poly silicon layer receives a reference ground voltage and is disposed on the buffer layer. The via array is disposed in the buffer layer and is used to electrically connect the metal layer and the poly silicon layer.

Abstract: The present disclosure provides a 3D memory structure such as 3D Flash memory structure applying for 3D AND flash memory and a method of forming the same. An etching stop layer is formed on a substrate including active elements. A stacked layer is formed on the etching stop layer. The stacked layer includes insulation layers and sacrificed layers stacked alternatively on the etching stop layer. A patterning process is performed on the stacked layer to form a first stacked structure above the active elements, a second stacked structure surrounding the first stacked structure, and a trench pattern separating the first stacked structure and the second stacked structure and exposing the etching stop layer. The trench pattern includes asymmetric inner sidewalls and outer sidewalls. The inner sidewalls define sidewalls of the first stacked structure. The outer sidewalls define sidewalls of the second stacked structure that face the first stacked structure.

Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

Abstract: A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

Abstract: An embodiment of the present disclosure provides a memory device. The memory device comprises a substrate. A plurality of word line layers are disposed over the substrate. An array of vertical NOR columns is in a first area of the plurality of word line layers. Each vertical NOR column in the array of vertical NOR columns includes a first conductive pillar and a second conductive pillar. Each vertical NOR column comprises a first plurality of memory cells arranged in a NOR configuration formed at cross points of word line layers in the plurality of word line layers with the first and second conductive pillars. An array of vertical NAND columns is in a second area of the plurality of word line layers. Each vertical NAND column in the array of vertical NAND columns includes a memory pillar. Each vertical NAND column comprises a second plurality of memory cells arranged in a NAND configuration formed at cross points of word line layers in the plurality of word line layers with the memory pillar.

Abstract: Provided is a method of forming a three-dimensional (3D) memory device including: forming a discharging layer and a stack structure on a buffer layer; forming vertical channel structures in the stack structure; forming an opening in the stack structure, wherein the opening includes two first trenches extending along a X direction and two second trenches extending along a Y direction, and the two first trenches and the two second trenches are separated from each other; forming an insulating layer on a sidewall of the opening; removing the discharging layer exposed by the insulating layer to form a cavity connecting the two first trenches and the two second trenches, thereby forming a ring-shaped opening; performing a gate replacement process to replace sacrificial layers of the stack structure by conductive layers; and filling an isolating material in the ring-shaped opening to form an isolating ring structure.

Abstract: A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

Abstract: A memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

Abstract: A memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

Abstract: A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure.

Abstract: A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure.

Abstract: A touch keyboard including a keyboard pattern and a touch module is provided. A sensing space is located in front of the keyboard pattern. The touch module is disposed at periphery of the keyboard pattern. The touch module includes a light-emitting element, a light guide unit, and an optical detector. The light-emitting element is disposed beside the keyboard pattern and capable of emitting a light beam. The light guide unit is disposed at a side of the keyboard pattern and has a first surface, a second surface, and a light incident surface. The light beam from the light-emitting element is capable of entering the light guide unit through the light incident surface and capable of being transmitted to the sensing space through the first surface. The optical detector is disposed beside the sensing space for sensing the light beam from the sensing space. An electronic device is also provided.