Abstract: Method and device for compression bonding are disclosed. During compression bonding a chip to a substrate, an anti-adhesion layer on a stage is provided to contact with a solder resist layer on the substrate. The solder resist layer will not stick to the anti-adhesion layer such that the reduction of bonding precision due to the solder resist layer remains residues on the compression bonding device is preventable.

Abstract: Method and device for compression bonding are disclosed. During compression bonding a chip to a substrate, an anti-adhesion layer on a stage is provided to contact with a solder resist layer on the substrate. The solder resist layer will not stick to the anti-adhesion layer such that the reduction of bonding precision due to the solder resist layer remains residues on the compression bonding device is preventable.

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract: A wafer dicing method comprises providing a wafer and performing a cutting procedure and a contacting procedure. The wafer includes a plurality of dies and a metal layer, wherein the metal layer is formed on a scribe line which is formed between adjacent dies. A cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of dies on the wafer, and the metal layer cut by the cutter remains a plurality of metal burrs on the dies. A brush is used to contact with the metal burrs along the cutting slot during the contracting procedure to prevent each of the metal burrs from protruding from a surface of each of the dies.

Abstract: A wafer dicing method comprises providing a wafer and performing a cutting procedure and a contacting procedure. The wafer includes a plurality of dies and a metal layer, wherein the metal layer is formed on a scribe line which is formed between adjacent dies. A cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of dies on the wafer, and the metal layer cut by the cutter remains a plurality of metal burrs on the dies. A brush is used to contact with the metal burrs along the cutting slot during the contracting procedure to prevent each of the metal burrs from protruding from a surface of each of the dies.

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

Abstract: A semiconductor package process includes the following steps, providing a first substrate having a first metal bump, the first metal bump comprises a joint portion having a first softening point; providing a second substrate having a second metal bump having a top surface, a lateral surface and a second softening point, wherein the first softening point is smaller than the second softening point; performing a heating procedure to make the joint portion of the first metal bump become a softened state; and laminating the first substrate on the second substrate to make the second metal bump embedded into the joint portion in the softened state to make the top surface and the lateral surface of the at least one second metal bump being clad extendedly by compressing the joint portion in the softened state.

Abstract: A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.

Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

Abstract: A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.

Abstract: A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.

Abstract: A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.

Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.

Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess.

Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.