Abstract: A multi-domain vertical alignment (MVA) liquid crystal display panel includes an array substrate, a color filter (CF) substrate arranged in parallel to the array substrate, a plurality of bump patterns disposed on the CF substrate, and a plurality of transparent electrode patterns disposed on the array substrate. Each bump pattern includes a main bump corresponding to a pixel region, and at least one bump wing corresponding to a scan line or a data line. Each main bump includes a first protrusion connected to a side of the main bump. Each transparent electrode pattern includes a main slit. The transparent electrode pattern further includes a plurality of fine slits disposed in an inner side and in an outer side of the main slit. The fine slits disposed in the outer side of the main slit near the data line have different lengths.

Abstract: A structure of embedded memory unit with loader comprises a main memory area and an information area as a part of the main memory area. A plurality of loader-program parts is dispersedly stored in different addresses of the main memory area, wherein the loader-program parts are combined to form a complete loader. A loader mapping area is used to store the loader-program during the boot stage. When the boot sequence starts, the original information stored in the loader mapping area is temporarily backup to a temporary space; and the released space is used to store the loader-program. After the boot sequence is completed, the original information is moved back to the original location.

Abstract: A clock generating method and circuit are provided. The circuit includes a basic clock unit, a plurality of subclock units, which are connected in parallel or in series, and a plurality of special control units (SCU). The basic clock unit provides a basic clock signal and each of the clock units provides a corresponding clock signal. Each of the special control units are disposed between two adjacent clock units to delay the clock signal generated by the clock unit connected to the output terminal of the special control units.